{"id":29878,"date":"2020-02-26T17:54:39","date_gmt":"2020-02-26T17:54:39","guid":{"rendered":"https:\/\/silvaco.com\/uncategorized\/soi-technology\/"},"modified":"2021-08-04T22:27:50","modified_gmt":"2021-08-05T05:27:50","slug":"soi-technology","status":"publish","type":"post","link":"https:\/\/silvaco.com\/ja\/published-papers\/soi-technology\/","title":{"rendered":"SOI Technology"},"content":{"rendered":"
\n

SOI Technology<\/h1>\n

The full text most of these papers may be found at the IEEE website at\u00a0www.ieee.org.<\/a><\/p>\n

Ali A. Orouji, Hamid Amini Moghadam, A. Dideban,
\n“Double window partial SOI-LDMOSFET: A novel device for breakdown voltage improvement”,
\nPhysica E: Low-dimensional Systems and Nanostructures, In Press, Accepted Manuscript, Available online 21 September 2010.<\/p>\n

Michelly de Souza, Denis Flandre, Marcelo Antonio Pavanello,
\n“Analysis of source-follower buffers implemented with graded-channel SOI nMOSFETs operating at cryogenic temperatures”,
\nCryogenics, Vol. 49, Issue 11, November 2009, pp. 599-604.<\/p>\n

Rupendra Kumar Sharma, Ritesh Gupta, Mridula Gupta, R.S. Gupta,
\n“Dynamic performance of graded channel DG FD SOI n-MOSFETs for minimizing the gate misalignment effect”,
\nMicroelectronics Reliability, Vol. 49, Issue 7, July 2009, pp. 699-706<\/p>\n

N. A. B. A. Rahim, M. H. B. Abdullah, M. Rusop,
\n“Performance analysis of Si3N4 capping layer and SOI technology in sub 90 nm PMOS device”,
\nAIP Conference Proceedings, Vol. 1136, 2009, pp. 770-774<\/p>\n

S. M. F. Bin Syed Adrus, M. H. Bin Abdullah, M. Rusop,
\n“Electrical analysis of 65 nm PMOS based on SOI technology”,
\nAIP Conference Proceedings, Vol. 1136, 2009, pp. 775-780<\/p>\n

Michelly de Souza, Denis Flandre, Marcelo Antonio Pavanello,
\n“Analysis of source-follower buffers implemented with graded-channel SOI nMOSFETs operating at cryogenic temperatures Cryogenics”,
\nIn Press, Corrected Proof, Available online 3 January 2009<\/p>\n

D. Munteanu1<\/sup>, S. Cristoloveanu1<\/sup>\u00a0and E. Guichard2<\/sup>,
\n“3D Numerical Simulation of the Pseudo-MOS Transistor for SOI Film Characterization”
\n1<\/sup>LPCS\/ENSERG, 23 rue des Martyrs BP 257, F-38016 Grenoble Cedex\u00a01<\/sup>, France
\n2<\/sup>Silvaco Data System Sarl, 8, av. de Vignate 38610 Gi\u00e8res France<\/p>\n

Maria Gl\u00f3ria Ca\u00f1o de Andrade, Jo\u00e3o Antonio Martino,
\n“Threshold voltages of SOI MuGFETs”,
\nSolid-State Electronics, Vol. 52, Issue 12, December 2008, pp. 1877-1883<\/p>\n

Michelly de Souza, Denis Flandre, Marcelo Antonio Pavanello,
\n“Advantages of graded-channel SOI nMOSFETs for application as source-follower analog buffer”,
\nSolid-State Electronics, Vol. 52, Issue 12, December 2008, pp. 1933-1938<\/p>\n

Chi-Woo Lee, Dimitri Lederer, Aryan Afzalian, Ran Yan, Nima Dehdashti, Weize Xiong, Jean-Pierre Colinge,
\n“Comparison of contact resistance between accumulation-mode and inversion-mode multigate FETs”,
\nSolid-State Electronics, Vol. 52, Issue 11, November 2008, pp. 1815-1820<\/p>\n

Chung Ha Suh,
\n“A simple analytical model for the front and back gate threshold voltages of a fully-depleted asymmetric SOI MOSFET”,
\nSolid-State Electronics, Vol. 52, Issue 8, August 2008, pp. 1249-1255<\/p>\n

Jean-Paul Mazellier, Olivier Faynot, Sorin Cristoloveanu, Simon Deleonibus, Philippe Bergonzo,
\n“Integration of diamond in fully-depleted silicon-on-insulator technology as buried insulator: A theoretical analysis Diamond and Related Materials”,
\nVol. 17, Issues 7-10, July-October 2008, pp. 1248-1251<\/p>\n

H.P. Zhang, L. L. Sun, L. F. Jiang, L. Y. Xu, M. Lin,
\n“Process simulation of trench gate and plate and trench drain SOI nLDMOS with TCAD tools”,
\nSemiconductor Electronics, 2008. ICSE 2008.
\nIEEE International Conference on 25-27 Nov. 2008 pp. 92 – 95<\/p>\n

K. Modzelewski, R. Chintala, H. Moolamalla, S. Parke, D. Hackler,
\n“Design of a 32 nm independently-double-gated FlexFET SOI transistor”,
\n2008 17th Biennial University\/Government\/Industry Micro\/Nano Symposium, pp. 64-7, 2008<\/p>\n

Chung Ha Suh,
\n“A simple analytical model for the front and back gate threshold voltages of a fully-depleted asymmetric SOI MOSFET”,
\nSolid-State Electronics, In Press, Corrected Proof, Available online 14 July 2008<\/p>\n

Jean-Paul Mazellier, Olivier Faynot, Sorin Cristoloveanu, Simon Deleonibus, Philippe Bergonzo,
\n“Integration of diamond in fully-depleted silicon-on-insulator technology as buried insulator: A theoretical analysis Diamond and Related Materials”,
\nIn Press, Corrected Proof, Available online 3 April 2008<\/p>\n

Tang Junxiong, Tang Minghua, Yang Feng, Zhang Junjie, Zhou Yichun, Zheng Xuejun,
\n“A temperature-dependent model for threshold voltage and potential distribution of fully depleted SOI MOSFETs”
\nChinese Journal of Semiconductors, Vol 29, No. 1, Jan. 2008, pp. 45-49<\/p>\n

A. Kranti et al.,
\n“How crucial is gate misalignment for low\u2013Voltage operation in double gate SOI MOSFETs?”,
\nIn Proc. Fourth Workshop of the Thematic Network on Silicon on Insulator technology, devices and circuits (EuroSOI 2008), Cork, Ireland, 2008<\/p>\n

Rashmi et al.,
\n“Influence of gate\u2013underlap design on the performance of 6T\u2013SRAM cell with double gate SOI MOSFETs”,
\nIn Proc. Fourth Workshop of the Thematic Network on Silicon on Insulator technology, devices and circuits (EuroSOI 2008), Cork, Ireland, 2008<\/p>\n

B. Vincent, J. -F. Damlencourt, P. Rivallin, E. Nolot, C. Licitra, Y. Morand and L. Clavelier,
\n“Fabrication of SiGe-on-insulator substrates by a condensation technique: an experimental and modelling study”
\n30 January 2007 Semiconductor Science and Technology Vol. 22, Issue 3, art. no. 011, pp. 237-244<\/p>\n

E. Simoen, C. Claeys, T.M. Chung, D. Flandre, M.A. Pavanello, J.A. Martino and J.-P. Raskin,
\n“The low-frequency noise behaviour of graded-channel SOI nMOSFETs”,
\nSolid-State Electronics, Vol. 51, Issue 2, February 2007, pp. 260-267<\/p>\n

Feixia Yu and Ming-C. Cheng,
\n“Electrothermal simulation of SOI CMOS analog integrated circuits”,
\nSolid-State Electronics, Vol. 51, Issue 5, May 2007, pp. 691-702<\/p>\n

Oana Moldovan, Antonio Cerdeira, David Jim\u00e9nez, Jean-Pierre Raskin, Valeria Kilchytska, Denis Flandre, Nadine Collaert and Benjamin I\u00f1iguez,
\n“Compact model for highly-doped double-gate SOI MOSFETs targeting baseband analog applications”,
\nSolid-State Electronics, Vol. 51, Issue 5, May 2007, pp. 655-661<\/p>\n

Toru Tsuboyama, Yasuo Arai, Koichi Fukuda, Kazuhiko Hara, Hirokazu Hayashi, Masashi Hazumi, Jiro Ida, Hirokazu Ikeda, Yoichi Ikegami, Hirokazu Ishino, Takeo Kawasaki, Takashi Kohriki, Hirotaka Komatsubara, Elena Martin, Hideki Miyake, Ai Mochizuki, Morifumi Ohno, Yuuji Saegusa, Hiro Tajima, Osamu Tajima, et al.,
\n“R&D of a pixel sensor based on 0.15um fully depleted SOI technology”,
\nNuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment, Vol. 582, Issue 3, 1 December 2007, pp. 861-865<\/p>\n

Tao Chuan Lim and G. Alastair Armstrong,
\n“Scaling issues for analogue circuits using Double Gate SOI transistors”,
\nSolid-State Electronics, Vol. 51, Issue 2, February 2007, pp. 320-327<\/p>\n

Chung Tsung Ming, Raskin,
\n“DC AND AC ANALYSES OF NOVEL SOI MOSFET DEVICES USING 2D AND 3D NUMERICAL SIMULATIONS”
\nJean-Pierre International Journal of Nanoscience. Vol. 5, No. 4-5, pp. 639-644. Aug. & Oct. 2006<\/p>\n

A. Kranti et al.,
\n“DGSOI \u2013 from the OTA perspective”,
\nIn Proc. Seventh European Workshop on Ultimate Integration of Silicon \u2013 ULIS 2006, Grenoble, France, pp. 53-54, 2006<\/p>\n

Tsung Ming Chung, Jean-Pierre Raskin,
\n“DC AND AC Analyses of Novel SOI Mosfet Device Using 2D AND 3D Nunmerical Simulation”
\nInternational Journal of Nanoscience, Vol. 5, Nos. 4-5 (2006) 639-644<\/p>\n

Gimenez, S. P., Ferreira, R. M. G., Martino, J. A.,
\n“Early Voltage behavior in circular gate SOI nMOSFET using 0.13 \u00ce1\u20444m partially-depleted SOI CMOS technology”
\n2006 ECS Transactions 4 (1), pp. 309-318<\/p>\n

Kranti, A., Armstrong, G. A.,
\n“Compact model for short channel effects in source\/drain engineered nanoscale Double Gate (DG) SOI MOSFETs”
\nNSTI Nanotech 2006 Technical Proceedings 3, pp. 820-823<\/p>\n

Joseph Ervin, Asha Balijepalli, Punarvasu Joshi, Vadim Kushner, Jinman Yang,
\nTrevor J. Thornton
\n“CMOS-Compatible SOI MESFETs With High Breakdown Voltage”
\nElectron Devices, IEEE Transactions on Vol. 53, Issue 12, Dec. 2006 pp. 3129-3135<\/p>\n

A. Kranti et al.,
\n“Optimization of source\/drain extension region profile for suppression of short channel effects in sub-50 nm DG MOSFET with high gate dielectrics”,
\nSemiconductor Science and Technology, Vol. 21, no. 12, pp. 1563-1572, 2006<\/p>\n

T.C. Lim et al.,
\n“Performance assessment of nanoscale multiple gate MOSFETs (MuGFETs) for rf applications”,
\nEuropean Microwave Integrated Circuits (EuMIC) Conference 2006, Manchester, UK, pp. 308-311, 2006<\/p>\n

A. Kranti et al.,
\n“Optimal design of source\/drain extension (SDE) regions in multiple gate MOSFETs”,
\nIn Proc. Seventh European Workshop on Ultimate Integration of Silicon \u2013 ULIS 2006, Grenoble, France, pp. 137-140, 2006<\/p>\n

A. Kranti et al.,
\n“Modelling short channel effects in source\/drain extension region engineered double gate MOSFETs”,
\nIn Proc. Second Workshop of the Thematic Network on Silicon on Insulator Technology \u2013 EuroSOI 2006, Grenoble, France, pp. 131-132, 2006<\/p>\n

M.S. Alam et al.,
\n“Analogue performance of double gate SOI transistors”,
\nInternational Journal of Electronics, Vol. 93, no. 1, pp. 1-18, 2006<\/p>\n

T.C. Lim et al.,
\n“Parameter sensitivity for optimal design of 25nm double gate SOI transistors”,
\nSolid-State Electronics, Vol. 49, no. 6, pp, 1034-1043, 2005<\/p>\n

T. C. Lim and G. A. Armstrong,
\n“Parameter sensitivity for optimal design of 65nm node double gate SOI transistors”
\nSolid-State Electronics, Vol. 49, Issue 6, June 2005, pp. 1034-1043<\/p>\n

V. Kilchytska, D. Levacq, L. Vancaillie, D. Flandre,
\n“On the great potential of non-doped MOSFETs for analog applications in partially-depleted SOI CMOS process”
\nSolid-State Electronics, Vol. 49, Issue 5, May 2005, pp. 708-715<\/p>\n

M. J. Lee, J. H. Cho, S. D. Lee, J. H. Ahn, J. W. Kim, S. W. Park, Y. J. Park, H. S. Min,
\n“Partial SOI type isolation for improvement of DRAM cell transistor characteristics”
\nIEEE Electron Device Letters, Vol. 26, Issue 5, May 2005, pp. 332-334<\/p>\n

D. Lederer, J.-P. Raskin,
\n“Effective resistivity of fully-processed SOI substrates”
\nSolid-State Electronics, Vol. 49, Issue 3, March 2005, pp. 491-496<\/p>\n

M. Wiatr, P. Seegebrecht,
\n“Impact of floating silicon film on small-signal parameters of fully depleted SOI-MOSFETs biased into accumulation”
\nSolid-State Electronics, Vol. 49, Issue 5, May 2005, pp. 779-789<\/p>\n

K. Nishiguchi, H. Inokawa, Y. Ono, A. Fujiwara, Y. Takahashi,
\n“Multifunctional Boolean logic using single-electron transistors”
\nIEICE Transactions on Electronics, Vol. E87-C, Issue 11, November 2004, pp. 1809-1817<\/p>\n

B. Ashcroft, B. Takulapalli, J. Yang, G. M. Laws, H. Q. Zhang, N. J. Tao, S. Lindsay, D. Gust, T. J. Thornton,
\n“Calibration of a pH sensitive buried channel silicon-on-insulator MOSFET for sensor applications”,
\nPhysica Status Solidi (b), Vol. 241, Issue 10, Aug. 2004, pp. 2291-2296<\/p>\n

N. V. T. D’Halleweyn, J. Benson, W. Redman-White, K. Mistry, M. Swanenberg,
\n“MOOSE: A physically based compact DC model of SOI LDMOSFETs for analogue circuit simulation”
\nIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 23, Issue 10, October 2004, pp. 1399-1410<\/p>\n

S. Mitra, A. Salman, D. P. Ioannou, C. Tretz, D. E. Ioannou,
\n“Double gate (DG)-SOI ratioed logic with symmetric DG load – A novel approach for sub 50 nm low-Voltage\/low-power circuit design”
\nSolid-State Electronics, Vol. 48, Issue 10-11 SPEC. ISS., October 2004, pp. 1727-1732<\/p>\n

F. Yu and M. -C. Cheng,
\n“Application of heat flow models to SOI current mirrors”
\nSolid-State Electronics, Vol. 48, Issue 10-11 SPEC. ISS., October 2004, pp. 1733-1739<\/p>\n

J. Lin, M. Shen, M. -C. Cheng, M. L. Glasser,
\n“Efficient thermal modeling of SOI MOSFETs for fast dynamic operation”
\nIEEE Transactions on Electron Devices, Vol. 51, Issue 10, October 2004, pp. 1659-1666<\/p>\n

B. Ashcroft, B. Takulapalli, J. Yang, G. M. Laws, H. Q. Zhang, N. J. Tao, S. Lindsay, D. Gust, T. J. Thornton,
\n“Calibration of a pH sensitive buried channel silicon-on-insulator MOSFET for sensor applications”
\nPhysica Status Solidi (B) Basic Research, Vol. 241, Issue 10, August 2004, pp. 2291-2296<\/p>\n

S. S. Suryagandh, M. Garg, J. C. S. Woo,
\n“A device design methodology for sub-100-nm SOC applications using bulk and SOI MOSFETs”
\nIEEE Transactions on Electron Devices, Vol. 51, Issue 7, July 2004, pp. 1122-1128<\/p>\n

A. Kranti, T. M. Chung, D. Flandre, J. -P Raskin,
\n“Laterally asymmetric channel engineering in fully depleted double gate SOI MOSFETs for high performance analog applications”
\nSolid-State Electronics, Vol. 48, Issue 6, June 2004, pp. 947-959<\/p>\n

C. E. Png, S. P. Chan, S. T. Lim, et al.,
\n“Optical phase modulators for MHz and GHz modulation in silicon-on-insulator (SOI)”
\nJournal Of Lightwave Technology, Vol. 22, No. 6, June 2004, pp. 1573-1582<\/p>\n

Ching Eng Png, Seong Phun Chan, Soon Thor Lim, G. T. Reed,
\n“Optical phase modulators for MHz and GHz modulation in silicon-on-insulator (SOI)”
\nJournal of Lightwave Technology, Vol. 22, No. 6, June 2004, pp. 1573-82<\/p>\n

M. C. Cheng, F. Yu, L. Jun, M. Shen and G. Ahmadi,
\n“Steady-state and dynamic thermal models for heat flow analysis of silicon-on-insulator MOSFETs”
\nMicroelectron. Reliab., Vol. 44, Mar 2004, pp. 381-396<\/p>\n

M. C. Cheng, F. Yu, P. Habitz and G. Ahmadi,
\n“Analytical heat flow modeling of silicon-on-insulator devices”
\nSolid-State Electronics, Vol. 48, Mar 2004, pp. 415-426<\/p>\n

P. Pandey, B. B. Pal and S. Jit,
\n“A new 2-D model for the potential distribution and threshold Voltage of fully depleted short-channel Si-SOI MESFETs”
\nIEEE Trans. Electron Devices, Vol. 51, Feb 2004, pp. 246-254<\/p>\n

C. Aydin, A. Zaslavsky, S. Luryi, S. Cristoloveanu, D. Mariolle, D. Fraboulet, S. Deleonibus,
\n“Lateral interband tunneling transistor in silicon-on-insulator”
\nApplied Physics Letters, Vol. 84, Issue 10, 8 March 2004, pp. 1780-1782<\/p>\n

F. Allibert, J. Pretet, G. Pananakakis, S. Cristoloveanu,
\n“Transition from partial to full depletion in silicon-on-insulator transistors: Impact of channel length”
\nApplied Physics Letters, Vol. 84, Issue 7, February 2004, pp. 1192-1194<\/p>\n

W. -S. Son, S. -G. Kim, Y. -H. Sohn, S. -Y. Choi,
\n“A new SOI LDMOSFET structure with a trench in the drift region for a PDP scan driver IC”
\nETRI Journal, Vol. 26, Issue 1, February 2004, pp. 7-12<\/p>\n

F. Yu, M. -C. Cheng, P. Habitz, G. Ahmadi,
\n“Modeling of thermal behavior in SOI structures”
\nIEEE Transactions on Electron Devices, Vol. 51, Issue 1, January 2004, pp. 83-91<\/p>\n

G. T. Reed, G. Z. Masanovic, W. R. Headley, C. E. Png, S. P. Chan, S. T. Lim, V. M. N. Passaro, D. Hak, O. Cohen, M. Paniccia,
\n“Small devices in SOI: Fabrication and design issues”
\nProceedings of SPIE – The International Society for Optical Engineering, Vol. 5357, 2004, pp. 75-86<\/p>\n

C. E. Png, G. T. Reed, W. R. Headley, K. P. Homewood, A. Liu, M. Paniccia, R. M. H. Atta, G. Ensell, A. G. R. Evans, D. Hak, O. Cohen,
\n“Design and experimental results of small silicon-based optical modulators”
\nProceedings of SPIE – The International Society for Optical Engineering, Vol. 5356, 2004, pp. 44-55<\/p>\n

I. Ionica, L. Mont\u00e8s, S. Ferraton, J. Zimmermann, V. Bouchiat, L. Saminadayar,
\n“Silicon nanostructures patterned on SOI by AFM lithography”
\n2004 NSTI Nanotechnology Conference and Trade Show – NSTI Nanotech 2004, Vol. 3, 2004, pp. 165-168<\/p>\n

A. M. Ionescu, D. Munteanu, N. Hefyene, C. Anghel,
\n“Compact modeling of weak inversion generation transients in SOI MOSFETs”
\nJournal of the Electrochemical Society, Vol. 151, Issue 6, 2004<\/p>\n

C. E. Png, G. T. Reed, R. M. H. Atta, G. Ensell, A. G. R. Evans,
\n“Development of small silicon modulators in Silicon-On-Insulator (SOI)”
\nProceedings of SPIE – The International Society for Optical Engineering, Vol. 4997, 2003, pp. 190-197<\/p>\n

S. Mitra, A. Salman, D. P. Ioannou, C. Tretz and D. E. Ioannou,
\n“Low Voltage\/low power sub 50 nm double gate SOI ratioed logic”
\nIEEE International SOI Conference 2003, 29 Sep – 2 Oct 2003, pp. 177-178<\/p>\n

S. S. Suryagandh, M. Garg and J. C. S. Woo,
\n“A detailed analysis of SOI MOSFETs for SOC design”
\nIEEE International SOI Conference 2003, 29 Sep – 2 Oct 2003, pp. 147-148<\/p>\n

M Jagadesh Kumar and Vinod Parihar,
\n“A Novel High Current Gain Lateral PNP Transistor on SOI for Complimentary Bipolar Technology”
\nProc. of 2003 International Semiconductor Device Research Symposium, Washington DC, December 10-12 2003, ppg 268-269<\/p>\n

Feixia Yu and Ming-C Cheng,
\n“Heat Flow in SOI Current Mirrors”
\nProc. of 2003 International Semiconductor Device Research Symposium, Washington DC, December 10-12 2003, pp. 392-393<\/p>\n

A. Raman, D. G. Walker, T. S. Fisher,
\n“Simulation of nonequilibrium thermal effects in power LDMOS transistors”
\nSolid-State Electronics, Vol. 47, Issue 8, August 2003, pp. 1265-1273<\/p>\n

R. J. Luyken, T. Schulz, J. Hartwich, L. Dreeskornfeld, M. Stadele, W. Rosner,
\n“Design considerations for fully depleted SOI transistors in the 25-50 nm gate length regime”
\nSolid-State Electronics, Vol. 47, July 2003, pp. 1199-1203<\/p>\n

M. Jagadesh Kumar and C. Linga Reddy,
\n“2D-simulation and analysis of lateral SiC N-emitter SiGe P-base Schottky metal-collector (NPM) HBT on SOI”,
\nMicroelectronics Reliability, Vol. 43, Issue 7, July 2003, pp. 1145-1149<\/p>\n

M. Kittler, R. Granzner, F. Schwierz, W. Henschel, T. Wahlbrink, H. Kurz,
\n“Simulation and optimization of EJ-MOSFETs”
\nSolid-State Electronics, Vol. 47, July 2003, pp. 1193-1198<\/p>\n

Xiangli Li, S. A. Parke and B. M. Wilamowski,
\n“Threshold Voltage control for deep sub-micrometer fully depleted SOI MOSFET”
\nProceedings of the 15th Biennial University\/Government\/Industry Microelectronics Symposium 2003, 30<\/p>\n

T. H. Tan and A. K. Goel,
\n“Zero-temperature-coefficient biasing point of a fully-depleted SOI MOSFET”
\nMicrowave and Optical Technology Letters, Vol. 37, Jun. 2003, pp. 366 370<\/p>\n

M.-C. Cheng, R. Wettimuny, P. Habitz, G. Ahmadi,
\n“Thermal simulation for SOI devices using thermal-circuit models and device simulation”
\nSolid-State Electronics, Vol. 47, February 2003, pp. 345-351<\/p>\n

Niraj Subba, Souvick Mitra, Akram Salman and Dimitris E. Ioannou,
\n“Device physics considerations for SOI domino circuit design”
\nSolid-State Electronics, Vol. 47, Issue 2, Feb. 2003, pp. 175-179<\/p>\n

S. Mitra, A. Salman, D. P. Ioannou, C. Tretz, D. E. Ioannou,
\n“Low Voltage \/ Low Power sub 50 nm Double Gate SOI Ratioed Logic”
\nIEEE International SOI Conference, 2003, pp. 177-178<\/p>\n

S. Mitra, A. Salman, D. P. Ioannou, C. Tretz, D. E. Ioannou,
\n“DG-SOI ratioed logic with symmetric DG load – a novel approach for sub 50 nm LV\/LP circuit design”
\n2003 International Semiconductor Device Research Symposium (IEEE Cat. No.03EX741), 2003, pp. 390<\/p>\n

D. Munteanu, G. Le Carval, C. Fenouillet-B\u00e9ranger, O. Faynot,
\n“Investigation of nonstationary transport and quantum effects in realistic deep submicrometer partially depleted SOI technology”
\nElectrochemical and Solid-State Letters, Vol. 5, Issue 5, May 2002<\/p>\n

Jong-Tae Park and Jean-Pierre Colinge,
\n“Multiple-Gate SOI MOSFETs: Device Design Guidelines”
\nIEEE Trans. Elect. Devices, Vol. 49, Issue 12, Dec. 2002, pp. 2222-2229<\/p>\n

S. Adriaensen and D. Flandre,
\n“Analysis of the thin-film SOI lateral bipolar transistor and optimization of its output characteristics for high-temperature applications”
\nSolid-State Electronics, Vol. 46, Issue 9, Sep. 2002, pp. 1339-1343<\/p>\n

J. Yang, T. J. Thornton, M. Kozicki, L. de la Garza and D. Gust,
\n“Molecular control of the threshold Voltage of an NMOS inversion layer”
\nMicroelectronic Engineering, Vol. 63, Issues 1-3, Aug. 2002, pp. 135-139<\/p>\n

M. Dehan and J. -P. Raskin,
\n“An asymmetric channel SOI nMOSFET for improving DC and microwave characteristics”
\nSolid-State Electronics, Vol. 46, July 2002, pp. 1005-1011<\/p>\n

M. Jagadesh Kumar and D. Venkatesh Rao,
\n“A new lateral PNM Schottky collector bipolar transistor (SCBT) on SOI for nonsaturating VLSI logic design”
\nIEEE Trans. Electron Devices, Vol. 49, Jun. 2002, pp. 1070-1072<\/p>\n

C. Ravariu, A. Rusu, F. Ravariu, D. Dobrescu and L. Dobrescu,
\n“From -MOSFET with silicon on oxide to -MOSFET with silicon carbide on nitride”
\nDiamond and Related Materials, Vol. 11, Issues 3-6, Mar.-Jun. 2002, pp. 1268-1271<\/p>\n

J. Yang, T. J. Thornton, S. M. Goodnick, M. Kozicki and J. Lyding,
\n“Buried channel silicon-on-insulator MOSFETs for hot-electron spectroscopy”
\nPhysica B: Condensed Matter, Vol. 314, March 2002, pp. 354-357<\/p>\n

S. Mitra, A. Salman, D. P. Ioannou, D. E. Ioannou,
\n“LP\/LV ratioed DG-SOI logic with (intrinsically on) symmetric DG-MOSFET load”
\nIEEE International SOI Conference, 2002, pp. 66-67<\/p>\n

S. Adriaensen, V. Dessard, D. Flandre,
\n“A Voltage reference compatible with standard SOI CMOS processes and consuming 1pA to 50nA from room temperature up to 300”
\nIEEE International SOI Conference, 2002, pp. 130-131<\/p>\n

Jong-Jun Kim, Hwan-Sool Oh, Doo-Yeon Chung, and Jong-Ho Lee,
\n“Implementation of specific frequency response using SOI photodetector cell”
\nJournal of the Korean Physical Society, Vol. 40, No. 1, January 2002, pp. 34-38<\/p>\n

A. Cerdeira, M. Estrada, R. Quintero, D. Flandre, A. Ortiz-Conde and F. J. Garc\u00eda S\u00e1nchez,
\n“New method for determination of harmonic distortion in SOI FD transistors”
\nSolid-State Electronics, Vol. 46, Issue 1, Jan. 2002, pp. 103-108<\/p>\n

J. Pretet, D. Ioannou, N. Subba, S. Cristoloveanu, W. Maszara and C. Raynaud,
\n“Narrow-channel effects and their impact on the static and floating-body characteristics of STI- and LOCOS-isolated SOI MOSFETs”
\nSolid-State Electronics, Vol. 46, Issue 11, 2002, pp. 1699-1707<\/p>\n

D. Tomaszewski, L. Lukasiak, J. Gibki, K. Doman\u00b4ski, A. Jakubowski, A. Zarba,
\n“Measurement and modelling of SOI MOSFETs capacitances”
\nProceedings of SPIE – The International Society for Optical Engineering, Vol. 4746 I, 2002<\/p>\n

J\u00f6rgen Olsson,
\n“Self-heating effects in SOI bipolar transistors”
\nMicroelectronic Engineering, Vol. 56, Issues 3-4, August 2001, pp. 339-352<\/p>\n

E. Rauly, B. I\u00f1iguez, D. Flandre,
\n“Investigation of deep submicron single and double gate SOI MOSFETs in accumulation mode for enhanced performance”
\nElectrochemical and Solid-State Letters, Vol. 4, Issue 3, March 2001<\/p>\n

O. Faynot, T. Poiroux and J. L. Pelloie,
\n“Compact analytical modeling of SOI partially depleted MOSFETs with LETISOI”
\nSolid-State Electronics, Vol. 45, Issue 4, April 2001, pp. 599-605<\/p>\n

Mikael Johansson, Jonas Berg and Stefan Bengtsson,
\n“High frequency properties of silicon-on-insulator and novel depleted silicon materials”
\nSolid-State Electronics, Vol. 45, Issue 4, April 2001, pp. 567-573<\/p>\n

P. D. Hewitt and G. T. Reed,
\n“Improved modulation performance of a silicon p-i-n device by trench isolation”
\nJournal of Lightwave Technology, Vol. 19, Issue 3, March 2001, pp. 387-390<\/p>\n

J. Pretet, N. Subba, D. Ioannou, S. Cristoloveanu, W. Maszara, C. Raynaud,
\n“Explaining the reduced floating body effects in narrow channel SOI MOSFETs”
\nIEEE International SOI Conference, 2001, pp. 25-26<\/p>\n

S. Jit, P. Pandey, A. Kumar, S. K. Gupta,
\n“Modified boundary condition at Si-SiO2 interface for modeling of threshold Voltage and subthreshold swing of short-channel SOI MESFET\u00b4s”
\nSolid-State Electronics, Vol. 49, Issue 1, January 2005, pp. 141-143<\/p>\n

F. Yu, M. -C. Cheng,
\n“Thermal modeling of silicon-on-insulator current mirrors”
\nProc. – IEEE International SOI Conference, 2004, pp. 81-83<\/p>\n

Widiez J., Daug F., Vinet M., Poiroux T., Previtali B., Mouis M., Deleonibus S.,
\n“Experimental gate misalignment analysis on double gate SOI MOSFETs”
\nProc. – IEEE International SOI Conference, 2004, pp. 185-186<\/p>\n

J. Lolivier, J. Widiez, M. Vinet, T. Poiroux, F. Daug, B. Previtali, M. Mouis, J. Jommah, F. Balestra, S. Deleonibus,
\n“Experimental comparison between Double Gate, Ground Plane, and Single Gate SOI CMOSFETs”
\nESSCIRC 2004 – Proceedings of the 34th European Solid-State Device Research Conference, 2004, pp. 77-80<\/p>\n

J. Lolivier, M. Vinet, T. Poiroux, B. Previtali, T. CheVolleau, J. M. Hartmann, A. -M. Papon, R. Truche, O. Faynot, F. Balestra, S. Deleonibus,
\n“10nm-gate-Iength transistors on ultra-thin SOI film : Process realization and design optimisation”
\nProceedings – IEEE International SOI Conference, 2004, pp. 17-18<\/p>\n

T. C. Lim, N. D. Jankovic, G. A. Armstrong,
\n“Scaling of fully depleted SOI mosfets with P+poly sige gates”
\n10th International Symposium on Integrated Circuits, Devices and Systems, ISIC-2004: Integrated Sys pp. 20-21<\/p>\n

C. D. G. Dos Santos, M. A. Pavanello, J. A. Martino, D. Flandre, J. P. Raskin,
\n“Behavior of Graded Channel SOI Gate-All-Around nMOSFET devices at high temperatures”
\nElectrochemical Society Proceedings, Vol. 3, 2004, pp. 9-14<\/p>\n

T. Hoang, P. LeMinh, J. Holleman, V. Zieren, M. J. Goossens, J. Schmitz,
\n“A high efficiency lateral light emitting device on SOI”
\nThe 12th IEEE International Symposium on Electron Devices for Microwave and Optoelectronic Applications, EDMO, 8-9 November 2004<\/p>\n

H. W. Kim, S. C. Kim, K. S. Seo, W. Bahng, E. D. Kim,
\n“Device characteristics of the SOI LIGBT with dual-epi layers”
\nProc. – IPEMC 2004: 4th International Power Electronics and Motion Control Conference<\/p>\n

Ravariu C. Ravariu F. Rusu A. Dobrescu D. Dobrescu L.,
\n“The Modeling of a SOI Microelectromechanical Sensor”
\nProc. SISPAD 2001, pp. 328-331<\/p>\n

Park J-K., Deshpande H.V., Woo J.C.S.,
\n“The Effect of Impact Ionization on the subthreshold Leakage Current in N-Channel Double-Gated SOI Transistors”
\nProc. of the 31st European Solid-State Device Research Conference, September 2001, pp. 163-166<\/p>\n

M. Trivedi, P. Khandelwal, K. Shenai and S. K. Leong,
\n“Design and modeling of bulk and SOI power LDMOSFETs for RF wireless applications”
\nSolid-State Electronics, Vol. 44, Issue 8, 1 August 2000, pp. 1343-1354<\/p>\n

S. Cristoloveanu, D. Munteanu, and M.S.T. Liu,
\n“A review of the pseudo-MOS transistor in SOI wafers: operation, parameter extraction, and applications”
\nIEEE Transactions On Electron Devices, Vol. 47, Issue 5, May 2000, pp. 1018-1027<\/p>\n

P. D. Hewitt and G. T. Reed,
\n“Improving the response of optical phase modulators in SOI by computer simulation”
\nJournal of Lightwave Technology, Vol. 18, Issue 3, March 2000, pp. 443-450<\/p>\n

Rauly E. Iniguez B. Flandre D. Raynaud C.,
\n“Investigation of Single and Double Gate SOI MOSFETs in Accumulation Mode for Enhanced Performances and Reduced Technological Drawbacks”
\nProc. ESSDERC 2000, pp. 540-543<\/p>\n

A. Vandooren, S. Cristoloveanu, and J. P. Colinge,
\n“The dynamic conductance and transconductance in double-gate (gate-all-round) SOI devices”
\nProceeding of IEEE International SOI Conference, 2000, pp. 116-117<\/p>\n

E. Rauly, O. Potavin, F. Balestra, C. Raynaud,
\n“On the subthreshold swing and short channel effects in single and double gate deep submicron SOI-MOSFETs”
\nSolid-State Electronics, Vol. 43, November 1999, pp. 2033-2037<\/p>\n

T. Ernst, D. Munteanu, S. Cristoloveanu, T. Ouisse, S. Horiguchi, Y. Ono, Y. Takahashi and K. Murase,
\n“Investigation of SOI MOSFETs with Ultimate Thickness”
\nMicroelectronic Engineering, Vol. 48, Issues 1-4, September 1999, pp. 339-342<\/p>\n

Joonho Gil, Minkyu Je, Jongho Lee and Hyungcheol Shin,
\n“A high speed and low power SOI inverter using active body-bias”
\nSolid-State Electronics, Vol. 43, Issue 4, April 1999, pp. 791-799<\/p>\n

D. Munteanu, S. Cristoloveanu and E. Guichard,
\n“Numerical simulation of the pseudo-MOSFET characterization technique”
\nSolid-State Electronics, Vol. 43, Issue 3, March 1999, pp. 547-554<\/p>\n

P. D. Hewitt and G. T. Reed,
\n“Multi-micron dimension optical p-i-n phase modulators in silicon on insulator”
\nProceedings of SPIE, Vol. 3630, 1999, pp. 237-243<\/p>\n

Yang-Kyu Choi, K. Asano, N. Lindert, V. Subramanian, Tsu-Jae King, J. Bokor, and Chenming Hu,
\n“Ultra-thin body SOI MOSFET for deep-sub-tenth micron era”
\nIEEE International Electron Devices Meeting, IEDM Technical Digest, 1999, pp. 919-921<\/p>\n

T. Ernst, S. Cristoloveanu, et al.,
\n“Recombination current and carrier lifetime extraction in dual-gate fully depleted SOI devices”
\nProc. ESSDERC 1998, pp. 272-275<\/p>\n

A. M. Ionescu, A. Chovet and F. Chaudier,
\n“Junction influence on drain current transients in partially-depleted SOI MOSFETs”
\nElectron Letter, Vol. 33, Sep 1997, pp. 1740-1742<\/p>\n

Y. Fu, C. J. Patel and M. Willander,
\n“Quantum mechanical description of p-type Si\/Si1 – xGex quantum well mosfet in silicon-on-insulator technology”
\nSolid-State Electronics, Vol. 41, Issue 5, May 1997, pp. 729-732<\/p>\n

Th. Aeugle et al.,
\n“Advanced self aligned soi concepts for vertical MOS transistors with ultrashort channel lengths”
\nESSDERC’97, pp. 628-629<\/p>\n

F. Deng et al.,
\n“Salicide process for 400A fully depleted SOI-MOSFETs using NiSi”
\nProc. IEEE International SOI Conf., 1997, pp. 22-23<\/p>\n

J. A. Burns et al.,
\n“Design criteria for a fully depleted-0.1um SOI technology”
\nProc. IEEE International SOI Conf., 1997, pp. 78-79<\/p>\n

W. Rauly and F. Balestra
\n“Hot carrier effects in sub-0.1um SOI-MOSFETs”
\nProc. ESSDERC’97, pp. 344-345<\/p>\n

D. Munteanu, S. Cristoloveanu and E. Guichard
\n“3-D Numerical simulation of the pseudo-MOS transistor”
\nProc. IEEE International SOI Conf., 1997, pp. 94-95<\/p>\n

P. Perupalli et al.,
\n“Performance evaluation of bulk Si and SOI RF LDMOSFETs for emerging RFIC applications”
\nProc. IEEE International SOI Conf., 1997, pp. 108-109<\/p>\n

A. M. Ionescu, et al.,
\n“Modeling and 2D numerical Simulation of Transient Phenomena in Floating Body SOI MOSFETS”
\nibid, pp. 239<\/p>\n

R. B. Hulfachor, K. W. Kim, M. A. Littlejohn, C. M. Osburn,
\n“Non-Local Transport and 2-D Effects on Hot Electron Injection in Fully-Depleted 0.1 um SOI n-MOSFET’s Using Monte Carlo Simulation”
\nMicroelectronic Engineering, Vol. 28, Issues 1-4, June 1995, pp. 289-292<\/p>\n

D. A. Dallman et al.,
\n“Scaling Constraints Imposed by Self-heating in Submicron SOI MOSFET\u00b4S”
\nIEEE Trans. on Electron devices, Vol. 42, Issue 3, March 1995, pp 489-496<\/p>\n

Y. Apanovich, P. Blakey, R. Cottle, E. Lyumkis, B. Polsky, and A. Shur,
\n“Numerical simulation of ultra-thin soi transistor using non-isothermal energy balance model”
\nIEEE International SOI Conference, 3-6 Oct. 1994, Nantucket, MA, USA, pp. 33-40<\/p>\n

Y. Apanovich, E. Lyumkis, B. Polsky, and P. Blakey,
\n“Non-isothermal analysis of breakdown in soi transistors”
\nIEEE Transactions on Electron Devices, Vol. 40, Issue 11, November 1993, pp. 2094 – 2096<\/p>\n

Milda, Hasegawa, Hagiwara, Ohshiba,
\n“A CCD Video Delay Line With Charge-Integrating Amplifier”
\nIEEE Jour. Solidd State Circuits, December 1991, pp. 1915-1919<\/p>\n<\/div><\/section><\/div>

<\/div>