{"id":29874,"date":"2020-02-26T18:27:44","date_gmt":"2020-02-26T18:27:44","guid":{"rendered":"https:\/\/silvaco.com\/uncategorized\/power-device-simulation\/"},"modified":"2021-08-04T22:25:40","modified_gmt":"2021-08-05T05:25:40","slug":"power-device-simulation","status":"publish","type":"post","link":"https:\/\/silvaco.com\/ja\/published-papers\/power-device-simulation\/","title":{"rendered":"Power Device Simulation"},"content":{"rendered":"
\n

Power Device Simulation<\/h1>\n

The full text for most of these papers may be found at the IEEE website at\u00a0www.ieee.org<\/a>.<\/p>\n

Viviana Cerantonio, Marcello Giuffrida, Cristina Miccoli, Alessandro Chini, Ferdinando Iucolano
\n“From TCAD simulations to large signal model for GaN RF device<\/a>”<\/p>\n

Sang-Woo Han, Jianan Song, and Rongming Chu
\n“Design of GaN\/AlGaN\/GaN Super-Heterojunction Schottky Diode<\/a>”
\nIEEE Transactions On Electron Devices, Volume. 67, NO. 1, January 2020<\/p>\n

Cristina Miccoli, Ferdinando Iucolano
\n“Study of oxide trapping in SiC MOSFETs by means of TCAD simulations<\/a>,”
\nMaterials Science in Semiconductor Processing, Volume 97, July 2019, pp. 40-43<\/p>\n

Dondee Navarro1,2<\/sup>, Akihiro Tone1<\/sup>, Hideyuki Kikuchihara1<\/sup>, Yoji Morikawa2<\/sup>\u00a0and Mitiko Miura-Mattausch1<\/sup>
\n“Enhanced Miller plateau characteristics of a 4H-SiC insulated-gate bipolar transistor in the presence of interface traps<\/a>,”<\/p>\n

    \n
  1. Hiroshima University, 1-3-1 Kagamiyama, Higashi-Hiroshima 739-8530 Japan<\/li>\n
  2. Silvaco Japan, Yokohama Landmark Tower 36F, 2-2-1 Minatomirai, Nishi-ku, Yokohama 220-8136 Japan<\/li>\n<\/ol>\n

    Japanese Journal of Applied Physics, Volume 56, Number 4S, March 2017.<\/p>\n

    Man Hoi Wong1<\/sup>, Yoji Morikawa2<\/sup>, Kohei Sasaki3,1<\/sup>, Akito Kuramata3<\/sup>, Shigenobu Yamakoshi3<\/sup>, and Masataka Higashiwaki1<\/sup>
    \n“    Characterization of channel temperature in Ga2O3 metal-oxide-semiconductor field-effect transistors by electrical measurements and thermal modeling<\/a>,”<\/p>\n

      \n
    1. National Institute of Information and Communications Technology, 4\u20132\u20131 Nukui-Kitamachi, Koganei, Tokyo 184\u20138795, Japan<\/li>\n
    2. Silvaco Japan Co., Ltd., 2\u20132\u20131 Minatomirai, Nishi-ku, Yokohama, Kanagawa 220\u20138136, Japan<\/li>\n
    3. Tamura Corporation, 2\u20133\u20131 Hirosedai, Sayama, Saitama 350\u20131328, Japan<\/li>\n<\/ol>\n

      Applied Physics Letters vol. 109, pp. 193503 (2016).<\/p>\n

      Dondee Navarro1<\/sup>, Iliya Pesic1<\/sup>, Yoji Morikawa1<\/sup>, Yoshiharu Furui1<\/sup>, and Mitiko Miura-Mattausch2<\/sup>,
      \n“Investigation of 4H-SiC IGBT Turn-off Performance for Achieving Low Power Loss,”<\/p>\n

        \n
      1. Silvaco Japan, Yokohama Landmark Tower 36F, 2-2-1 Minatomirai, Nishi-ku, Yokohama 220-8136 Japan<\/li>\n
      2. Hiroshima University, 1-3-1 Kagamiyama, Higashi-Hiroshima 739-8530 Japan<\/li>\n<\/ol>\n

        Japanese Journal of Applied Physics (JJAP) Paper<\/a>
        \nJapanese Journal of Applied Physics, Vol. 55, 4S, 04ER12, March 2016.<\/p>\n

        International Conference on Solid State Devices and Materials (SSDM) 2015 Proceedings, pp. 502-503.
        \nCopyright 2015 The Japan Society of Applied Physics
        \nSSDM 2015 Poster<\/p>\n

        Iliya Pesic1,2<\/sup>, Dondee Navarro2<\/sup>, Masato Fujinaga2<\/sup>, Yoshiharu Furui2<\/sup>, and Mitiko Miura-Mattausch1<\/sup>,
        \n“Switching Characteristics of a 4H-SiC IGBT with Interface Defects Up to the Nonquasi-Static Regime,”<\/p>\n

          \n
        1. Hiroshima University, 1-3-1 Kagamiyama, Higashi-Hiroshima<\/li>\n
        2. Silvaco Japan, 4F Miyake Bldg, 549-2 Shinano-cho, Totsuka, Yokohama 244-0801 Japan<\/li>\n<\/ol>\n

          International Conference on Solid State Devices and Materials (SSDM) 2014, pp.376-377
          \nCopyright 2014 The Japan Society of Applied Physics<\/span><\/p>\n

          Lei Yong(\u96f7\u52c7)1; 2<\/sup>, Shi Hongbiao(\u77f3\u5b8f\u5f6a)1<\/sup>, Lu Hai(\u9646\u6d77)1<\/sup>, Chen Dunjun(\u9648\u6566\u519b)1<\/sup>, Zhang Rong(\u5f20\u8363)1<\/sup>, and Zheng Youdou(\u90d1\u6709\u7093)1<\/sup>,
          \n“Field plate engineering for GaN-based Schottky barrier diodes,”<\/p>\n

            \n
          1. Nanjing National Laboratory of Microstructures, Jiangsu Provincial Key Laboratory of Advanced Photonic and Electronic Materials, and School of Electronic Science and Engineering, Nanjing University, Nanjing 210093, China<\/li>\n
          2. School of Physics and Optoelectronic Engineering, Nanjing University of Information Science and Technology, Nanjing 210044, China
            \nCopyright 2014 The Japan Society of Applied Physics<\/span><\/li>\n<\/ol>\n

            Ying Wang, Hai-fan Hu, Cheng-hao Yu, and Hao Lan,
            \n“High-Performance Split-Gate Enhanced MOSFET With p-Pillar Structure,”
            \nIEEE ELECTRON DEVICE LETTERS<\/p>\n

            Marco Silvestri, Michael J. Uren, and Martin Kuball,
            \n“            Iron-induced deep-level acceptor center in GaN\/AlGaN high electron mobility transistors: Energy level and cross section<\/a>,”
            \nCenter for Device Thermography and Reliability (CDTR), H.H. Wills Physics Laboratory, University of Bristol, BS8 1TL Bristol, United Kingdom<\/p>\n

            Kazuhiro Mochizuki, Senior Member, IEEE, Tomoyoshi Mishima, Senior Member, IEEE, Akihisa Terano, Naoki Kaneda, Takashi Ishigaki, Member, IEEE, and Tomonobu Tsuchiya,
            \n“Numerical Analysis of Forward-Current\/Voltage Characteristics of Vertical GaN Schottky-Barrier Diodes and p-n Diodes on Free-Standing GaN Substrates”<\/p>\n

            Masataka Miyake1<\/sup>, Fumiya Ueno2<\/sup>, Dondee Navarro3<\/sup>, and Mitiko Miura-Mattausch2<\/sup>,
            \n“            Compact Modeling of the Punch-Through Effect in SiC-IGBT for 6.6kV Switching Operation with Improved Performance<\/a>,”
            \n1<\/sup>HiSIM Research Center, Hiroshima University, Higashihiroshima, Hiroshima 739\u20138530, Japan
            \n2<\/sup>Grad. Sch. of Advanced Sciences of Matter, Hiroshima Univ., Higashihiroshima, 739\u20138530, Japan
            \n3<\/sup>SILVACO Japan Co., Ltd., Yokohama, Kanagawa 244\u20130801, Japan
            \nSilicon Carbide and Related Materials (ECSCRM) 2012, Saint Petersburg, Russia
            \n            Poster<\/a><\/p>\n

            Ming Qiao, Xi Hu, Hengjuan Wen, Meng Wang, Bo Luo, Xiaorong Luo, Zhuo Wang, Bo Zhang and Zhaoji Li,
            \n“A Novel Substrate-Assisted RESURF Technology for Small Curvature Radius Junction,”
            \nProceedings of the 23rd International Symposium on Power Semiconductor Devices & IC’s May 23-26, 2011.<\/p>\n

            Dr Ivan Pesic,
            \n“Integrated Simulation Solution for Advanced Power Devices”
            \n8th International Workshop on Compact modeling, January 25, 2011 Yokohama Japan<\/p>\n

            C. Ronsisvalle, V. Enea, C. Abbate, G. Busatto, F. Iannuzzo, A. Sanseverino, G. A. P. Cirrone,
            \n“Effects of back-side He irradiation on MOS-GTO performances,”
            \nISPSD2011.<\/p>\n

            C. Ronsisvalle, V. Enea, C. Abbate, G. Busatto, A. Sanseverino,
            \n“Perspective performances of MOS_Gated GTO in High-Power Applications,”
            \nTrans. On Electron Dev., Vol. 57, Issue 9, September 2010, pp. 2339-2343.<\/p>\n

            Ying Wang, Chao Cheng, Hai-fan Hu,
            \n“Investigation of power Trench MOSFETs with retrograde body profile,”
            \nMicroelectronics Reliability, In Press, Corrected Proof, Available online 19 September 2010.<\/p>\n

            M. A. Bela\u00efd, K. Daoud,
            \n“Evaluation of hot-electron effects on critical parameter drifts in power RF LDMOS transistors,”
            \nMicroelectronics Reliability, Vol. 50, Issues 9-11, September-November 2010, pp. 1763-1767.<\/p>\n

            G. Busatto, G. Curr\u00f2, F. Iannuzzo, A. Porzio, A. Sanseverino, F. Velardi,
            \n“Experimental study and numerical investigation on the formation of single event gate damages induced on medium voltage power MOSFET,”
            \nMicroelectronics Reliability, Vol. 50, Issues 9-11, September-November 2010, pp. 1842-1847.<\/p>\n

            Nebojsa Jankovic, Petar Igic, Naoki Sakurai,
            \n“Compact model of the IGBTs with localized lifetime control dedicated to power circuit simulations,”
            \nSolid-State Electronics, Vol. 54, Issue 3, March 2010, pp. 268-274.<\/p>\n

            G. E. Vineyard,
            \n“Investigating the Electrothermal Characteristics of a Gate Turn Off Thyristor During Turn-Off Using SILVACO ATLAS(TM),”
            \nNaval Postgraduate School, Monterey, CA., Jun 2009, pp. 149.<\/p>\n

            R. S. Saxena and M. Jagadesh Kumar,
            \n“A New Buried-Oxide-In-Drift-Region Trench MOSFET With Improved Breakdown Voltage,”
            \nIEEE Electron Device Letters. Manuscript revised June 23, 2009. Accepted for inclusion in a future issue of this journal.<\/p>\n

            R. S. Saxena and M. Jagadesh Kumar,
            \n“A Stepped Oxide Hetero-Material Gate Trench Power MOSFET for Improved Performance,”
            \nIEEE Trans Electron Devices, Vol. 56, No. 6, June 2009, pp. 1355-1359.<\/p>\n

            O. Bengtsson, L. Vestling, J. Olsson,
            \n“A computational load-pull method with harmonic loading for high-efficiency investigations,”
            \nSolid-State Electronics, Vol. 53, Issue 1, January 2009, pp. 86-94.<\/p>\n

            Fortunato Pezzimenti, Francesco G. Della Corte, Roberta Nipoti,
            \n“Experimental characterization and numerical analysis of the 4H-SiC p\u2013i\u2013n diodes static and transient behaviour,”
            \nMicroelectronics Journal, Vol. 39, Issue 12, December 2008, pp. 1594-1599.<\/p>\n

            L. C. Yu, K. Sheng, J. H. Zhao,
            \n“Modeling and design of a monolithically integrated power converter on SiC,”
            \nSolid-State Electronics, Vol. 52, Issue 10, October 2008, pp. 1625-1630.<\/p>\n

            Yu. P. Snitovsky, V. V. Nelayev, V. A. Efremov,
            \n“New approach to the manufacturing of power microwave bipolar transistors: A computer simulation,”
            \nRussian Microelectronics, Vol. 36, No. 6, Nov. 2007, pp. 409-414.<\/p>\n

            Hua Ye, Changwoo Lee, James Raynolds, Pradeep Haldar, Michael J. Hennessy and Eduard K. Mueller,
            \n“Silicon power MOSFET at low temperatures: A two-dimensional computer simulation study”
            \nCryogenics, Vol. 47, Issue 4, April 2007, pp. 243-251.<\/p>\n

            Nebojsa Jankovic, Tatjana Pesic and Petar Igic,
            \n“All injection level power PiN diode model including temperature dependence,”
            \nSolid-State Electronics, Vol. 51, Issue 5, May 2007, pp. 719-725.<\/p>\n

            Guo Liang-Liang, Feng Qian, Hao Yue, Yang Yan,
            \n“Study of high breakdown-voltage AIGaN\/GaN FP-HEMT,”
            \nActa Physica Sinica, Vol. 56, No. 5, May 2007, pp. 2895-2899.<\/p>\n

            M. Alwan, B. Beydoun, K. Ketata and M. Zoaeter,
            \n“Bias temperature instability from gate charge characteristics investigations in N-Channel Power MOSFET,”
            \nMicroelectronics Journal, Vol. 38, Issues 6-7, June-July 2007, pp. 727-734.<\/p>\n

            M. Alwan, B. Beydoun, K. Ketata and M. Zoaeter,
            \n“Gate charge behaviors in N-channel power VDMOSFETs during HEF and PBT stresses,”
            \nMicroelectronics Reliability, Vol. 47, Issues 9-11, September-November 2007, pp. 1406-1410.<\/p>\n

            J. Vobeck\u00fd and P. Hazdra,
            \n“Dynamic avalanche in diodes with local lifetime control by means of palladium,”
            \nMicroelectronics Journal, In Press, Corrected Proof, Available online 21 December 2007.<\/p>\n

            Tintori O., Munteanu D., Loussier X., Autran J. L., Regnier A., Bouchakour R,
            \n“Compact modeling and performance analysis of Double-Gate MOSFET-based circuits,”
            \nNSTI Nanotechnology Conference and Trade Show – NSTI Nanotech 2006 Technical Proceedings 3, pp. 812-815.<\/p>\n

            M. A. Bela\u00efd, K. Ketata, K. Mourgues, M. Gares, M. Masmoudi and J. Marcon,
            \n“Reliability study of power RF LDMOS device under thermal stress”
            \n10 October 2006 Microelectronics Journal 38 (2 SPEC. ISS.), pp. 164-170.<\/p>\n

            M. Garesa, H. Maananea, M. Masmoudia, P. Bertramb, J. Marcona, M. A. Belaid, K. Mourguesa, C. Tolantb and P. Eudeline,
            \n“Hot carrier reliability of RF N- LDMOS for S Band radar application”
            \nMicroelectronics Reliability 46 (9-11), pp.1806-1811 September-November 2006.<\/p>\n

            C. L. Zhang, K. S. Jeon, C. H. Ahn, J. D. Park, E. D. Kim, Na Zhi, Yong Gao,
            \n“Integrated IC-like Thyristor\u2014based Switching Structure for Pulse Current Generation to Electronic Ignition,”
            \nPower Electronics and Motion Control Conference, 2006. IPEMC 2006. CES\/IEEE 5th International Volume 2, 14-16 Aug. 2006 pp. 1 – 4.<\/p>\n

            M. A. Belaid, K. Ketata, M. Gares, J. Marcon, K. Mourgues, M. Masmoudi,
            \n“2-D simulation and analysis of temperature effects on electrical parameters degradation of power RF LDMOS device,”
            \nNuclear Instruments & Methods in Physics Research, Section B (Beam Interactions with Materials and Atoms), Vol. 253, No. 1-2, Dec. 2006, pp. 250-254.<\/p>\n

            K. S. Kelkar, N. E. Islam, C. M. Fessler, W. C. Nunnally,
            \n“Investigation of Optically Initiated Avalanche Silicon Carbide High Power Switches,”
            \nConference Record of the Power Modulator Symposium, 2006. May 2006, pp. 252 – 255.<\/p>\n

            C. L. Zhang, K. S. Jeon, C. H. Ahn, J. D. Park, E. D. Kim, Na Zhi, Yong Gao,
            \n“Integrated IC-like Thyristory based Switching Structure for Pulse Current Generation to Electronic Ignition,”
            \nPower Electronics and Motion Control Conference, 2006. IPEMC ’06. CES\/IEEE 5th International Vol. 2, 14-16 Aug. 2006, pp. 1198-201.<\/p>\n

            A. Karabegovic, R. M. O’Connell,
            \n“Photoswitch-Controlled Class E RF Power Amplifier,”
            \nConference Record of the Power Modulator Symposium, 2006. 2006 Twenty-Seventh International. 14-18 May 2006, pp. 150 – 152.<\/p>\n

            De Orio, R. L. Swart, J. W, Marzano, W,
            \n“Design and simulation of a thyristor surge protective device for telecommunication systems”
            \nECS Transactions Vol. 4, Issue 1, 2006, pp. 319-326.<\/p>\n

            Z. Wang, A. T. Bryant, J. Wu, P. R. Palmer,
            \n“Implementation and Comparison of Power Diode Models for System Simulation,”
            \nInternational Conference on Power Electronics and Drives Systems, 2005. PEDS 2005. Vol. 1, Jan. 16-18, 2006, pp. 694 – 699.<\/p>\n

            P. Bhatnagar, A. B. Horsfall, N. G. Wright, C. M. Johnson, K. V. Vassilevski, A. G. O\u00b4Neill,
            \n“Optimisation of a 4H-SiC enhancement mode power JFET for high temperature operation”
            \nSolid-State Electronics, Vol. 49, Issue 3, March 2005, pp. 453-458.<\/p>\n

            K. S. Kelkar, N. E. Islam, C. M. Fessler, W. C. Nunnally
            \n“Silicon carbide photoconductive switch for high-power, linear-mode operations through sub-band-gap triggering”
            \nJournal of Applied Physics, Vol. 98, Issue 9, 1 November 2005, pp. 1-6.<\/p>\n

            R. K. Burra, S. K. Mazumder, R. Huang,
            \n“DV\/DT related spurious gate turn-on of bidirectional switches in a high-frequency cycloconverter”
            \nIEEE Transactions on Power Electronics, Vol. 20, Issue 6, November 2005, pp. 1237-1243.<\/p>\n

            G. M. Buiatti, F. Cappelluti, G. Ghione,
            \n“Finite Difference Based Power Diodes Simulation Within SPICE: Modeling Approach and Validation,”
            \nPower Electronics Specialists Conference, 2005. PESC ’05. IEEE 36th 2005, pp. 999 – 1003.<\/p>\n

            M. J. Kumar, V. Parihar,
            \n“Enhanced current gain in SiC power BJTs using a novel surface accumulation layer transistor concept”
            \nMicroelectronic Engineering, Vol. 81, Issue 1, July 2005, pp. 90-95.<\/p>\n

            B. Davenport and S. Michael,
            \n“Advanced thermophotovoltaic cells modeling, optimized for use in radioisotope thermoelectric generators (RTGs) for Mars and deep space missions”
            \nA Collection of the 22nd AIAA International Communications Satellite Systems Conference and Exhibit, 2004.<\/p>\n

            R. L. Thomas, M. Morgenstern, S. B. Bayne,
            \n“Silvaco modeling of a 10 kV SiC p-i-n diode”
            \nProceedings of the 26th International Power Modulator Symposium and 2004 High Voltage Workshop.<\/p>\n

            J. Ankarcrona, K. -H Eklund, L. Vestling, J. Olsson,
            \n“Simulation and modeling of the substrate contribution to the output resistance for RF-LDMOS power transistors”
            \nSolid-State Electronics, Vol. 48, Issue 5, May 2004, pp. 789-797.<\/p>\n

            M. Vellvehi, D. Flores, X. Jorda, S. Hidalgo, J. Rebollo, L. Coulbeck and P. Waind,
            \n“Design considerations for 6.5 kV IGBT devices”
            \nMicroelectronics Journal, Vol. 35, Mar. 2004, pp. 269-275.<\/p>\n

            H.-C. Cheng, F. -L. Chang, M. -J. Lin, C. -C. Tsai, C. W. Liaw,
            \n“Novel low-temperature polycrystalline-silicon power devices with very-low on-resistance using excimer laser-crystallization”
            \nJournal of the Electrochemical Society, Vol. 151, Issue 12, 2004.<\/p>\n

            C. -L. Wang, M. -H. Lai, S. -R. Huang, C. -Y. Yeh
            \n“Design of optimum the insulator Design of optimum the insulator gate bipolar transistor using response surface method with cluster analysis”
            \nJpn. J. Appl. Phys. Vol. 43, 2004, Part 1: Regular Papers and Short Notes and Review Papers.<\/p>\n

            S. Musumeci, R. Pagano, A. Raciti, G. Belverde, A. Magr\u00ec, M. Melito, F. Zara,
            \n“New packaging concepts and physics-based simulation approach for low-voltage power MOSFETs lead to performance improvement in advanced DC-DC converters”
            \nPESC Record – IEEE Annual Power Electronics Specialists Conference, Vol. 2, 2004, pp. 1531-1537.<\/p>\n

            S. C. Kim, H. W. Kim, K. S. Seo, C. L. Zhang, E. D. Kim,
            \n“Static and dynamic characteristics of the 2.5kV\/500A IGCTs”
            \nProceedings of the International Conference on Microelectronics, Vol. 24 I, 2004, pp. 171-173.<\/p>\n

            D. Frey, J. L. Schanen, J.L. Aug, O. Lesaint,
            \n“Electric field investigation in IGBT power modules”
            \nProceedings of the 2004 IEEE International Conference on Solid Dielectrics ICSD 2004, Vol. 2, pp. 1000-1005.<\/p>\n

            S. Azzopardi, J. M. Vinassa, E. Woirgard, C. Zardini, J. L. Aucouturier,
            \n“What can be the optimum IGBT structure under UIS operation?”
            \nPESC Record – IEEE Annual Power Electronics Specialists Conference, Vol. 4, 2004, pp. 2999-3003.<\/p>\n

            P. Hazdra, J. Vobecky, H. Dorschner, K. Brand,
            \n“Axial lifetime control in silicon power diodes by irradiation with protons, alphas, low- and high-energy electrons”
            \nMicroelectronics Journal, Vol. 35, Issue 3, March 2004, pp. 249 – 257.<\/p>\n

            Shuntao Hu and Kuang Sheng,
            \n“A New Edge Termination Technique for SiC Power Devices”
            \nProceedings of 2003 International Semiconductor Device Research Symposium, Washington DC, December 1, pp. 122-123.<\/p>\n

            James Fuerherm, Yu Anne Zeng, and Marvin H. White,
            \n“A Study of Interface Charges on the Operation of 4H Silicon Carbide Static (SiC) Static Induction Transistors (SITs)”
            \nProceedings of 2003 International Semiconductor Device Research Symposium, Washington DC, December 1, pp. 134-135.<\/p>\n

            S. Azzopardi, E. Woirgard, J. -M. Vinassa, O. Briat, C. Zardini,
            \n“IGBT Power modules thermal characterization: What is the optimum between a low current – High voltage or a high current – Low voltage test condition for the same electrical power?”
            \nMicroelectronics Reliability, Vol. 43, Issue 9-11, September 2003, pp. 1901-1906.<\/p>\n

            Il-Yong Park, et. al.,
            \n“Novel Process Technoques for Fabricating High Density Trench MOSFET with Self-Aligned N+\/P+ Source Formed on the Trench Side Wall”
            \nISPSD\u00b403 Proceedings, pp. 169-172.<\/p>\n

            Chanho Park et. al.,
            \n“Deep Trench Terminations Using ICP RIE for Ideal Breakdown Voltages”
            \nISPSD\u00b403 Proceedings, pp. 199-202.<\/p>\n

            S. Alves et. al.,
            \n“Vertical N-channel FLIMOSFET for Future 12V\/42V Dual Batteries Automotive Applications”
            \nISPSD\u00b403 Proceedings, pp. 308-311.<\/p>\n

            Timothy Henson and Joe Cao,
            \n“Low Voltage Superjunction MOSFET Simulation and Experiment”
            \nProc. International Symposium on Power Semiconductor Devices (ISPSD), 2003.<\/p>\n

            Xiangli Li, Huadian Pan and B. M. Wilamowski,
            \n“Gate-controlled punch through transistor Proceedings of the 15th Biennial University\/Government\/Industry”
            \nMicroelectronics Symposium 2003, 30 Jun-2 Jul 2003, pp. 226-229.<\/p>\n

            K. Kunihiro, Y. Takahashi, Y. Ohno,
            \n“Physical modeling of off-state breakdown in power GaAs MESFETs”
            \nSolid-State Electronics, Vol. 47, April 2003, pp. 621-631.<\/p>\n

            J. Vobecky, P. Hazdra, V. Zahlava,
            \n“Impact of the electron, proton and helium irradiation on the forward I-V characteristics of high-power P-i-N diode”
            \nMicroelectronics Reliability, Vol. 43, April 2003, pp. 537-544.<\/p>\n

            R. S. Anand, B. Mazhari and J. Narain,
            \n“A study into the applicability of p+n+ (universal contact) to power semiconductor diodes for faster reverse recovery”
            \nSolid-State Electronics, Vol. 47, Issue 1, Jan. 2003, pp. 83-91.<\/p>\n

            P. Cova, R. Menozzi and M. Portesine,
            \n“Power p-i-n diodes for snubberless application: H+ irradiation for soft and reliable reverse recovery”
            \nMicroelectronics Reliability, Vol. 43, Issue 1, Jan. 2003, pp. 81-87.<\/p>\n

            K. Kelkar and W. C. Nunnally,
            \n“Semiconductor Modeling for Multi-layer, High Field, Photo-Switch using sub-bandgap Photons”
            \nDigest of Technical Papers-IEEE International Pulsed Power Conference, 2003, pp. 819-822.<\/p>\n

            “Low Voltage Super Junction MOSFET Simulation and Experimentation”,
            \nTimothy Henson, Joe CaoInternational Rectifier, 233 Kansas St, El Segundo, CA 90245 USA, Phone +01 310 726 8842, Fax +01 310 726 8847 E-mail: thenson1@irf.com<\/p>\n

            X. Gu, Q. Shui, C. W. Myles, M. A. Gundersen
            \n“Comparison of Si, GaAs, SiC and GaN FET-type switches for pulsed power applications”
            \nDigest of Technical Papers-IEEE International Pulsed Power Conference, 2003, pp. 362-365<\/p>\n

            K. Shenai, C. Cavallaro, S. Musumeci, R. Pagano, A. Raciti,
            \n“Modeling Low-Voltage Power MOSFETs as Synchronous Rectifiers in Buck Converter Applications”
            \nConference Record – IAS Annual Meeting (IEEE Industry Applications Society), Vol. 3, 2003.<\/p>\n

            D. Frey, J. L. Schanen, J. L. Aug, J. L., Lesaint, O.,
            \n“Electric field investigation in high voltage power modules using finite element simulations and partial discharge measurements”
            \nConference Record – IAS Annual Meeting (IEEE Industry Applications Society), Vol. 2, 2003, pp. 1000-1005.<\/p>\n

            M. Vellvehi, D. Flores, X. Jord,
            \n“Design and optimisation of suitable edge terminations for 6.5 kV IGBTs”
            \nMicroelectronics Journal, Vol. 33, Issue 9, September 2002, pp. 765-769.<\/p>\n

            K. Shenai, M. Trivedi and P. Neudeck,
            \n“Characterization of Hard- and Soft-Switching Performance of High-Voltage Si and 4H-SiC PiN Diodes”
            \nIEEE Trans. Elect Dev. Sept 2002, pp. 1648-1656.<\/p>\n

            C. L. Wang,
            \n“Design of Optimum Power Insulated-Gate Bipolar Transistor Using Response Surface Method”
            \nJpn. J. Appl. Phys., Vol. 41, May 2002, pp. 2864-2872.<\/p>\n

            C. Tolksdorf, C. Fink, J. Schulze, S. Sedlmaier, W. Hansch, W. Werner, W. Kanert and I. Eisele,
            \n“The vertical concept of power MOSFETs”
            \nMaterials Science and Engineering B, Vol. 89, February 2002, pp. 439-443.<\/p>\n

            J. H. Kim et. al.,
            \n“High Performance Complementary Bipolar Process using PBSOI Technique”
            \nISPSD\u00b402 Proceedings, pp. 85-88.<\/p>\n

            Chanho Park et. al.,
            \n“A New Junction Termination Technique Using ICP RIE for Ideal Breakdown Voltages”
            \nISPSD\u00b402 Proceedings, pp. 257-260.<\/p>\n

            C. K. Jeon, et. al.,
            \n“Analysis of LDMOS Structure with Inclined P-bottom Region”
            \nISPSD\u00b402 Proceedings, pp. 293-296.<\/p>\n

            P. Hazdra, J. Vobecky and K. Brand,
            \n“Optimum lifetime structuring in silicon power diodes by means of various irradiation techniques”
            \nNucl. Instrum. Meth. B., Vol.186, Jan. 2002, pp. 414-418.<\/p>\n

            H. Hakim, J. -L. Sanchez, J. -P. Laur, P. Austin, M. Breil,
            \n“The concave junction: An attractive topology to design specific junction terminations”
            \nIEEE International Symposium on Power Semiconductor Devices and ICs (ISPSD), 2002, pp. 193-196.<\/p>\n

            A. Raman, D. G. Walker, T. S. Fisher,
            \n“Non-equilibrium thermal effects in power transistors”
            \nAmerican Society of Mechanical Engineers, Heat Transfer Division, (Publication) HTD, Vol. 369, Is.<\/p>\n

            S. Abedlnpour and K. Shenai,
            \n“Stress analysis of DC-DC power converters”
            \nProceedings of the Intersociety Energy Conversion Engineering Conference, Vol. 1, 2001, pp. 141.<\/p>\n

            S. Abedinpour, R. Burra, K. Shenai,
            \n“Two-dimensional finite element simulation and stress analysis of a full bridge DC-DC power converter”
            \nINTELEC, International Telecommunications Energy Conference (Proceedings), 2001, pp. 205-212.<\/p>\n

            M. J. Urena, D. Leea, B. T. Hughesa et al.,
            \n“Electrical characterization of AlGaN\/GaN heterostructure wafers for high-power HFETs”
            \nJournal of Crystal Growth, Vol. 230, 2001, pp. 579 – 583.<\/p>\n

            C. Fink, J. Schulze, I. Eisele, W. Hansch, W. Werner, W. Kanert,
            \n“Reducing of ROn in vertical Power-MOSFETs due to local channel doping”
            \nJapanese Journal of Applied Physics, 2001, Vol. 40, Issue 4B, pp. 2637.<\/p>\n

            K. Shenai,
            \n“High-power robust semiconductor electronics technologies in the new millennium”
            \nMicroelectronics Journal, Vol. 32, Issues 5-6, 2001, pp. 397-408.<\/p>\n

            G. Kamoulakos, Th. Haniotakis, Y. Tsiatouhas, J. -P. Schoellkopf and A. Arapoyanni,
            \n“Device simulation of a n-DMOS cell with trench isolation”
            \nMicroelectronics Journal, Vol. 32, Issue 1, January 2001, pp. 75-80.<\/p>\n

            C. Anghel, N. Hefyene, A. Ionescu, M. Vermandel, B. Bakeroot, J.Doutreloigne, R. Gillon, S. Frere, C. Maier, Y. Mourier,
            \n“Investigations and Physical Modelling of Saturation Effects in Lateral DMOS Transistor Architectures Based on the Concept of Intrinsic Drain Voltage”
            \nESSDERC 2001. pp. 399-402.<\/p>\n

            Kim S. L. Jeon C. K. Kim J. J. Choi Y. S. Kim M. H. Kang H. S. Song C. S.,
            \n“A New Compact Isolation Structure in High Side Island Region of 600V HVIC,”
            \nProc. ESSDERC 2001, pp. 415-418.<\/p>\n

            Frere S.F. Rhayem J. Adawe H.O. Gillon R. Tack M. Walton A.J.,
            \n“LDMOS Capacitance Analysis versus Gate and Drain Biases, Based on Comparison Between TCAD Simulations and Measurements,”
            \nProc. ESSDERC 2001, pp. 219-222.<\/p>\n

            Tsai-Sheng Liao, P. Yu, and O. Zucker,
            \n“Analysis of high pulse power generation using novel excitation of IGBT,”
            \nProceedings of the IEEE 6th International Conference on Solid-State and Integrated-Circuit Technology, Vol. 1. pp. 143-148.<\/p>\n

            Q. Zhang and T. S. Sudarshan
            \n“Lateral current spreading in SiC schottky diodes using metal overlap edge termination,”
            \nSolid-State Electronics, Vol. 45, 2001, pp. 1847-1850.<\/p>\n

            C. K. Jeon, J. J. Kim, Y. S. Choi, M. H. Kim, S. L. Kim, H. S. Kang, C. S. Song,
            \n“800V\/1A, 1-chip process for battery charger IC,”
            \nIEEE International Symposium on Power Semiconductor Devices and ICs (ISPSD), 2001, pp. 355-358.<\/p>\n

            Marc C. Tarplee et al.,
            \n“Design Rules for Field Plate Edge Termination in SiC Schottky Diodes,”
            \nIEEE Trans. Elect. Dev., Vol. 48, No. 12, Dec. 2001, pp. 2659-2664.<\/p>\n

            Q. Zhang and T. S. Sudarshan,
            \n“Lateral current spreading in SiC Schottky diodes using metal overlap edge termination”
            \nSolid-State Electronics, Vol. 45, Issue 10, October 2001, pp. 1847-1850.<\/p>\n

            N. L. Rupesinghe, M. Chhowalla, K. B. K. Teo, G. A. J. Amaratunga
            \n“Field emission vacuum power switch using vertically aligned carbon nanotubes”
            \nJournal of Vacuum Science and Technology B: Microelectronics and Nanometer Structures, 2001, Vol. 21, pp. 3-4.<\/p>\n

            D. Dragomirescu, G. Charitat,
            \n“Improving the dynamic avalanche breakdown of high voltage planar devices using semi-resistive field plates”
            \nMicroelectronics Journal, Vol. 32, May-June 2001, pp. 473-479.<\/p>\n

            P. D. Hewitt and G. T. Reed,
            \n“Improved modulation performance of a silicon p-i-n device by trench isolation”
            \nJournal of Lightwave Technology, Vol. 19, Issue 3, March 2001, pp. 387-390.<\/p>\n

            C. J. Hung, P. Roblin, and S. Akhtar,
            \n“Distributed b-spline electrothermal models of thyristors proposed for circuit simulation of power electronics”
            \nIEEE Transactions On Electron Devices, 48(2):353-366, February 2001.<\/p>\n

            B. You, A. Q. Huang, J. K. O. Sin,
            \n“A 600-V, 10-A trench bipolar junction diode with superior static and dynamic characteristics”
            \nIEEE Transactions on Electron Devices, Vol. 48, Issue 9, September 2001, pp. 2143-2147.<\/p>\n

            N. Cezac, F. Morancho, P. Rossel, H. Tranduc, A. Peyre-Lavigne
            \n“New generation of power MOSFET based on the concept of `Floating Islands\u00b4”
            \nEPJ Applied Physics, Vol. 10, Issue 3, June 2000, pp. 203-209.<\/p>\n

            K. Shenai, E. McShane, S. K. Leong, (sub T on fT title)
            \n“Lateral RF SOI power MOSFETs with fT of 6.9 GHz”
            \nIEEE Electron Device Letters, Vol. 21, Issue 10, October 2000, pp. 500-502.<\/p>\n

            K. Shenai and M. Trivedi,
            \n“Silicon carbide power electronics for high temperature applications”
            \nIEEE Aerospace Conference Proceedings, Vol. 5, 2000, pp. 431-437.<\/p>\n

            E. McShane and K. Shenai,
            \n“Microwave performance of power MOSFETs on SOI substrates”
            \nProceedings of the IEEE Cornell Conference on Advanced Concepts in High Speed Semiconductor Devices, pp. 148-157.<\/p>\n

            S. Azzopardi, M. Trivedi, C. Zardini and K. Shenai,
            \n“Non-destructive extraction of technological parameters for numerical simulation of conventional planar punch-through IGBT”
            \nSolid-State Electronics, Vol. 44, Issue 11, 1 November 2000, pp. 1899-1908.<\/p>\n

            I. M. Gordion, Z. S. Gribnikov, V. A. Korobov and V. V. Mitin,
            \n“Fast gate turn-off in a merged thyristor-like structure”
            \nSolid-State Electronics, Vol. 44, Issue 10, 1 October 2000, pp. 1723-1732.<\/p>\n

            M. Trivedi and K. Shenai,
            \n“Practical limits of high-voltage thyristors on wide band-gap materials”
            \nJournal of Applied Physics, Vol. 88, Issue 12, 15 December 2000, pp. 7313-7320.<\/p>\n

            K. Sheng, F. Udrea and G. A. J. Amaratunga,
            \n“Optimum carrier distribution of the IGBT”
            \nSolid-State Electronics, Vol. 44, Issue 9, 1 September 2000, pp. 1573-1583.<\/p>\n

            J. Vobecky, P. Hazdra, O. Humbel and N. Galster,
            \n“Crossing point current of electron and proton irradiated power P-i-N diodes”
            \nMicroelectronics Reliability, Vol. 40, Issue 3, 17 March 2000, pp. 427-433.<\/p>\n

            M. Hossin, C. M. Johnson, N. G. Wright and A. G. O\u00b4Neill,
            \n“Evaluation of GaAs Schottky gate bipolar transistor (SGBT) by electrothermal simulation”
            \nSolid-State Electronics, Vol. 44, Issue 1, January 2000, pp. 85-94.<\/p>\n

            P. D. Hewitt and G. T. Reed,
            \n“Improving the response of optical phase modulators in SOI by computer simulation”
            \nJournal of Lightwave Technology, Vol. 18, Issue 3, March 2000, pp. 443-450.<\/p>\n

            F. Z. Mezroua and R. Abid,
            \n“Two-dimensional simulation of the transient electrothermal effects during the gate turn-off thyristor turn-off”
            \nJournal of Vac. Sci. Technol. A, Vol. 18, Issue 2, 2000, pp. 787 – 792.<\/p>\n

            Changli Zhang, J. Waldmeyer, P. Roggwiller, Zhiming Chen, and Yapeng Lu,
            \n“Soft recovery characteristics of punch-through power diodes by proton irradiation”
            \nProceedings of the 3rd IEEE International Symposium on Power Electronics and Motion Control, 2000, Vol. 1. pp. 229-234.<\/p>\n

            P. B. Shah, K. A. Jones, A. K. Agarwal, and S. Seshadri,
            \n“In-depth analysis of SiC GTO thyristor performance using numerical simulations”
            \nSolid-State Electronics, Vol. 44, 2000, pp. 353-358.<\/p>\n

            A. Vandooren, S. Cristoloveanu, and J. P. Colinge,
            \n“The dynamic conductance and transconductance in double-gate (gate-all-round) SOI devices”
            \nProceeding of IEEE International SOI Conference, 2000, pp. 116-117.<\/p>\n

            Vermandel L. Doutreloigne J. Moens P Tack M.,
            \n“Using the Self Aligned Field Implant To Design High Voltage Devices in Sub-um CMOS Technologies”
            \nProc. ESSDERC 2000, pp. 228-231.<\/p>\n

            N. Cezac et al.,
            \n“A new generation of power unipolar devices: the concept of the floating islands MOS transistor (FLIMOST)”
            \nISPSD\u00b42000, Toulouse, pp. 69-72.<\/p>\n

            C. Finkl et al.,
            \n“Vertical Power-MOSFETs with Local Channel Doping”
            \nProc. IEDM 2000, pp. 71-74.<\/p>\n

            Vickram R. Vathulya and Marvin H. White,
            \n“Characterization and performance comparison of the power DIMOS structure fabricated with a reduced thermal budget in 4H and 6H-SiC”
            \nSolid-State Electronics, Vol. 44, Issue 2, 2000, pp. 309-315.<\/p>\n

            B. H. Stark and P. P. Palmer,
            \n“Switching aspects of hybrid semiconductor power devices”
            \nIEE Colloquium (Digest), Issue 30, 1999.<\/p>\n

            N. S. Saks, S. S. Mani, A. K. Agarwal, M. G. Ancona,
            \n“475-V high-voltage 6H-SiC lateral MOSFET”
            \nIEEE Electron Device Letters, Vol. 20, Issue 8, August 1999, pp. 431-433.<\/p>\n

            B. H. Stark and P. R. Palmer,
            \n“Single-gated multiple-mode power semiconductor devices”
            \nIEE Colloquium (Digest), Issue 104, 29 June 1999, pp. 21-24.<\/p>\n

            N. Ota, et al.,
            \n“Thick and large area PIN diodes for hard X-ray astronomy”
            \nNuclear Instruments and Methods in Physics Research A, Vol. 436, October 1999, pp. 291-296.<\/p>\n

            Budong You, Alex Q. Huang and Johnny K. O. Sin,
            \n“Analysis of high-voltage trench bipolar junction diode (TBJD)”
            \nSolid-State Electronics, Vol. 43, Issue 9, September 1999, pp. 1777-1783.<\/p>\n

            V. R. Vathulya, H. L. Shang and M. H. White,
            \n“A novel 6H-SiC power DMOSFET with implanted P-well spacer”
            \nIEEE Electron Device Letter, Vol. 20, Issue 7, Jul. 1999, pp. 354-356.<\/p>\n

            Vobeck\u00fd J., Hazdra P., Z\u00e1hlava, V.,
            \n“Open circuit voltage decay lifetime of ion irradiated devices”
            \nMicroelectronics Journal, Vol. 30, Issue 6, June 1999, pp. 513-520.<\/p>\n

            Z. S. Gribnikov, A. B. Brailovsky and V. V. Mitin,
            \n“Stacked PIN diode structures for microwave switching”
            \nSolid-State Electronics, Vol. 43, Issue 5, May 1999, pp. 997-1000.<\/p>\n

            P. R. Palmer and B. H. Stark,
            \n“Formalised method for effecting multiple modes in single MOS gated power devices”
            \nIEE Proceedings on Circuits, Devices and Systems, Vol. 146, Issue 4, 1999, pp. 203-209.<\/p>\n

            Yang-Kyu Choi, K. Asano, N. Lindert, V. Subramanian, Tsu-Jae King, J. Bokor, and Chenming Hu,
            \n“Ultra-thin body SOI MOSFET for deep-sub-tenth micron era”
            \nIEEE International Electron Devices Meeting, IEDM Technical Digest, Vol. 21, Issue 5, 1999, pp. 254-255.<\/p>\n

            H. T. Lim, F. Udrea, D. M. Garner, and W. I. Milne,
            \n“Modelling of self-heating effect in thin SOI and partial SOI LDMOS power devices”
            \nSolid-State Electronics, Vol. 43, Issue 7, 1999, pp. 1267-1280.<\/p>\n

            P. Hower et al.,
            \n“Safe Operating Area Considerations in LDMOS transistors”
            \nProc. ISPSD\u00b499, pp. 55-58.<\/p>\n

            Malay Trivedi and Krishna Shenai,
            \n“Physical Analysis Of Current Snap-Back Phenomenon In Buffered High Power Rectifiers”
            \nProc. IEEE BCTM 1999.<\/p>\n

            K. Palser et al.,
            \n“3D numerical simulation for assisting external latch-up protection test structure design”
            \nESSDERC 1999, Vol. 1, pp. 508-511.<\/p>\n

            Budong You et al.,
            \n“A New Trench Bipolar Junction Diode (TBJD)”
            \nProc. ISPSD 1999, pp. 133-136.<\/p>\n

            J. L.Sanchez et al.,
            \n“A new high-voltage integrated switch : the <> function”
            \nISPSD 1999, pp. 157-160.<\/p>\n

            Malay Trivedi and Krishna Shenai,
            \n“Comparison of RF Performance of Vertical and Lateral DMOSFET”
            \nISPSD 1999, pp. 245-248.<\/p>\n

            V. Raineri, M. Saggio, F. Frisina and E. Rimini,
            \n“Voids in silicon power devices”
            \nSolid-State Electronics, Vol. 42, December 1998, pp. 2295-2301.<\/p>\n

            Pankaj B. Shah and Kenneth A. Jones,
            \n“Two dimensional numerical investigation of the impact of material parameter uncertainty on the steady-state performance of passivated 4H-SiC thyristors”
            \nJournal of Applied Physics, Vol. 84, No. 8, October 1998, pp. 4625-4630.<\/p>\n

            M. Trivedi, A. Mulay, R. Vijayalakshmi, and K. Shenai,
            \n“MixedMode Simulation of Power Electronic Converters”
            \nDepartment of Electrical Engineering & Computer Science, 1135 SED University of Illinois at Chicago, Chicago, IL 60607<\/p>\n

            E. McShane, Y. Xu, P. Khandelwal, and K. Shenai,
            \n“Low-Power Systems-on-a-Chip CAD”
            \nDepartment of Electrical Engineering & Computer Science, 1135 SED
            \nUniversity of Illinois at Chicago,, Chicago, IL 60607<\/p>\n

            Eric Vandenbossche, Catherine De Keukeleire, Marc de Wolf, Hugo Van Hove and Johan Witters,
            \n“Modelling and simulation of hot-carriers degradation of high voltage floating lateral NDMOS transistors”
            \nMicroelectronics and Reliability, Vol. 38, Issues 6-8, 8 June 1998, pp. 1097-1101.<\/p>\n

            Miribel-Catala P. L., Puig-Vidal M., Bota S., Montane E.,
            \n“Metodologias de diseno fisico aplicadas al diseno de circuitos integrados de potencia (Physical design methodologies applied to the design of integrated power circuits)”
            \nInformacion Tecnologica, Vol. 9, Issue 2, 1998, pp. 319-322 (In Spanish).<\/p>\n

            P. R. Walsh, A. F. J.Murray and W. A. Lane,
            \n“A Family of Novel Surge Protection Devices With Improved Parameter Control”
            \nProceedings of 1998 ISPSD, pp. 301-305.<\/p>\n

            M. Nemoto, Y. Takahashi, T. Fujii, N. Iwamuro and Y. Seki,
            \n“Study on Voltage Oscillation Phenomenon in High power P-i-N Diode”
            \nProceedings of 1998 ISPSD, pp. 305-308.<\/p>\n

            M. T. Rahimo, D. E.Crees, N. Y. Shammas,
            \n“A Novel Concept for Fast Recovery Diodes having Junction Charge Extraction(JCE) Regions”
            \nProceedings of 1998 ISPSD, pp. 309-312.<\/p>\n

            M. Kataoka, K. Komuro, K. Fujita, M. Hayama, A. Taniguchi,
            \n“Analysis of Al-shorted WSix<\/sub>\/Si Gate Performance in High-Frequency Band Si Power MOSFETs with Process\/Device\/Circuit Continous Simulation”
            \nProceedings of 1998 ISPSD, pp. 333-336.<\/p>\n

            J. Wang and B. W. Williams,
            \n“A simulation study of high voltage 4H-SiC IGBTs”
            \nSemiconductor Science and Technology, Vol. 13, N. 7, 1998, pp. 806-815.<\/p>\n

            Francesco G. Della Cortea, Fortunato Pezzimentia, Roberta Nipotib,
            \n“”Simulation and Experimental Results on the Forward J\u2013V Characteristic of Al Implanted 4H\u2013SiC p\u2013i\u2013n Diodes””,
            \naDIMET\u2014Faculty of Engineering, Mediterranea University of Reggio Calabria, Via Graziella<\/p>\n

            J. Vobecky and P. Hazdra,
            \n“”Simulation of Ion Irradiated Power Devices in ATLAS””
            \nCzech Technical University in Prague, Department of Microelectronics, Czech Republic<\/p>\n

            M. Vermandel, C. De Backere and A. Van Calster,
            \n“A high voltage nDMOS structure in a standard sub-micron CMOS process”
            \nProc. ESSDERC 1997, pp. 508-511.<\/p>\n

            C. M. Johnson, M. Hossin and A. G. O\u00b4Neill
            \n“GaAs schottky gate bipolar transistor for high voltage power switching applications”
            \nProc. ESSDERC\u00b497, pp. 548-551.<\/p>\n

            B. You, A. Q. Huang, B. Zhang, Y. Li
            \n“The Bipolar Junction Diode (BJD) – A new power diode concept”
            \nInternational Power Electronics Congress – CIEP, Vol. 1998, 1998, pp. 164-169.<\/p>\n

            S. Azzopardi, J-M. Vinassa and C. Zardini,
            \n“Investigations on the internal physical behaviour of 600V punch-through IGBT under latch-up at high temperature”
            \nProc. ESSDERC 1997, pp. 616-619.<\/p>\n

            C. Mingues and G .Charitat,
            \n“Efficiency of junction termination techniques vs oxide trapped charges”
            \nProc. IEEE ISPSD 1997, pp.137-140.<\/p>\n

            S. Xu et al.,
            \n“BiLBRT: Bidirectional lateral base resistance controlled thyristor”
            \nProc. IEEE ISPSD 1997, pp. 281-284.<\/p>\n

            “M. Trivedi, S. Pendharkar, K. Shenai,
            \n“Switching characteristics of MCT\u00b4s and IGBT\u00b4s in power converters”
            \nIEEE Transactions on Electron Devices, Vol. 43, Issue 11, November 1996, pp. 1994-2003.<\/p>\n

            M. Allenspach, C. Dachs, G. H. Johnson and et al.,
            \n“SEGR and SEB in N-channel power MOSFETs”
            \nIEEE Trans. Nuclear Science, Vol. 43, Issue 6, Dec. 1996, pp. 2927-2931.<\/p>\n

            D. Uffmann, J. Ackermann, J. Stemmer, J. Aderhold, and H.-U. Schr\u00f6der
            \n“Temperature Dependence of Latch-up Holding Point for Majority Carrier Guards up to 250\u00b0C”
            \nLaboratorium f\u00fcr Informationstechnologie, Universit\u00e4t Hannover Schneiderberg 32, D-30167 Hannover, Germany<\/p>\n

            J. L. Titus, C. F. Wheatley, M. Allenspach and et al.,
            \n“Influence of ion beam energy on SEGR failure thresholds of vertical power MOSFETs”
            \nIEEE Trans. Nuclear Science, Vol. 43, Issue 6, Dec. 1996, pp. 2938-2943.<\/p>\n

            Ralph (Sam) Smith III, Raytheon Electronic Systems
            \n“Analysis of the Effect of Etchpit Defects on Breakdown Voltage”<\/p>\n

            M. Trivedi and K. Shenai,
            \n“Internal dynamics of IGBT during short circuit switching”
            \nProc. IEEE BCTM 1996, pp. 77-80.<\/p>\n

            D. Moncoqut et al.,
            \n“LDMOS Transistor for SMART POWER circuits: Modelling and design”
            \nProc. IEEE BCTM 1996, pp. 216-219.<\/p>\n

            A. Nezar et al.,
            \n“Hot-electron induced snapback in 50-V LDMOS transistors fabricated in 0.8 um CMOS technology”
            \nProc. IEEE BCTM\u00b496, pp. 224-226.<\/p>\n

            Francis K. Chai, S. L. Kosier, R. D. Schrimpf and K. F. Galloway,
            \n“A method for predicting breakdown voltage of power devices with cylindrical diffused junctions”
            \nSolid-State Electronics, Vol. 38, Issue 8, August 1995, pp. 1547-1549.<\/p>\n

            Widjaja, Kurnia, Shenai, Divan,
            \n“Switching Dyamics of IGBT\u00b4s in Soft-Switching Converters”
            \nIEEE Trans. on ED, Vol 42, Issue 3, March 1995, pp. 445-454.<\/p>\n

            Fischer K. J., Shenai K.,
            \n“Effect of Bipolar Turn-On on the Static Current-Voltage Characteristics of Scaled Vertical Power DMOSFET\u00b4s”
            \nIEEE Trans. on ED, Vol 42, Issue 3, March 1995, pp. 555-563.<\/p>\n

            S. L. Kosier et al.,
            \n“Comparison of termination methods for low-voltage, vertical integrated power devices”
            \nSolid States Electronics, Vol. 37, No 9, pp. 1611-1617 1994.<\/p>\n

            Widjaja, Kurnia, Divan, Shenal,
            \n“Computer Simulation and Design Optimization of IGBT\u00b4s in Soft-Switching Converters (note: references Silvaco\u00b4s MIXEDMODE)”
            \nISPSD, 1994.<\/p>\n

            A. F. J. Murray and W. A. Lane,
            \n“800V wiring for HVIC applications using polysilicon field plates”
            \nProc. ESSDERC\u00b494, pp. 213-216.<\/p>\n

            Y. Apanovich, R. Cottle, E. Lyumkis, B. Polsky, A. Shur, A. Tcherniaev, and P. Blakey,
            \n“Breakdown Simulation of Semiconductor Devices Including Energy Balance and Lattice Heating”
            \nWorkshop on Computational Elect, 1994.<\/p>\n

            Li, Crandle, Temkin, Hopper,
            \n“A Two-Dimensional Model for Silicide Growth”
            \nVPAD, 1993.<\/p>\n

            Park, M. Law,
            \n“A Point Defect Based 2D Model of Dislocation Loops & Their Effects on OED of Boron in Silicon”
            \nTECHCON, 1993.<\/p>\n

            Hellstrom, Freydin, Velmre, Udal,
            \n“Two-Dimensional Modeling of Self-Heating Processes in Semiconductor Structures”
            \nESD Symposium, 1993.<\/p>\n

            Parks, M. E. Law,
            \n“A Two-Dimensional Model of Dislocation Loops in Silicon”
            \nProcess Physics Symp Hawaii, 1993.<\/p>\n

            Meng, Chen, Robinson, Law, Slinkman, Jones,
            \n“Using Oxidation to Study the Reaction Between Point Defects & Dislocation Loops”
            \nProcess Physics Symp Hawaii, 1993.<\/p>\n

            Mark Law,
            \n“SUPREM-IV Seminar 1993”<\/p>\n

            Y. Apanovich, R. Cottle, B. Freydin, E. Lyumkis, B. Polsky, A., and P. Blakey,
            \n“Numerical Modeling of Electrothermal Effects in Semiconductor Devices”
            \nSISDEP, 1993.<\/p>\n

            Y. Apanovich, R. Cottle, B. Freydin, E. Lyumkis, B. Polsky, A. Tchernaiev, and P. Blakey,
            \n“The influence of lattice heating on semiconductor device characteristics”
            \nCOMPEL: The International Journal for Computation and Mathematics in Electrical and Electronic Engineering 1993 Vol. 12 Issue: 4 pp. 531 – 539.<\/p>\n

            Dunham,
            \n“A Quantitative Model for the Coupled Diffusion of Phosphorus & Pint Defects in Silicon”
            \nJ. Electrochem Soc. Vol 139. Issue. 9, pp. 2628-2636, Sept 1992.<\/p>\n

            Freydin, Velmere, Udal,
            \n“Failure Prediction of Power Devices Under Reverse Surge Current Conditions”
            \nISPSD, 1992.<\/p>\n

            Freydin, Velmere, Udal,
            \n“Electrothermal Simulation of Power Semiconductor Devices”
            \nVPAD, 1991.<\/p>\n

            Rabkin, Shabanov,
            \n“Modeling the Switching-Off Process in Latching p-n-p-n Structures Using A Quasi-Two-Dimensional Approximation”
            \nRadiotekhnika, 1989.<\/p>\n

            Rabkin, Korsmik,
            \n“Investigation of the Influence of the Parameters of the p-Bases on the Static Characteristics of a Latching Thyristor”
            \nRadiotekhnika, 1989.<\/p>\n

            Rabkin,
            \n“Mathematical Model & Investigation of the Turn-off Process of p-n-p-n Structures in Combination Regime”
            \nRadiotekhnika, 1989.<\/p>\n<\/div><\/section><\/div>

            <\/div>