{"id":29840,"date":"2019-08-29T16:54:31","date_gmt":"2019-08-29T16:54:31","guid":{"rendered":"https:\/\/silvaco.com\/uncategorized\/where-circuit-simulation-model-files-come-from\/"},"modified":"2021-08-04T22:40:55","modified_gmt":"2021-08-05T05:40:55","slug":"where-circuit-simulation-model-files-come-from","status":"publish","type":"post","link":"https:\/\/silvaco.com\/ja\/blog\/where-circuit-simulation-model-files-come-from\/","title":{"rendered":"Where Circuit Simulation Model Files Come From"},"content":{"rendered":"<div id='template_overview'  class='avia-section main_color avia-section-small avia-no-border-styling  avia-bg-style-scroll  avia-builder-el-0  avia-builder-el-no-sibling   container_wrap fullsize' style='background-color: #ffffff;  margin-top:0px; margin-bottom:0px; '  ><div class='container' ><main  role=\"main\" itemprop=\"mainContentOfPage\"  class='template-page content  av-content-full alpha units'><div class='post-entry post-entry-type-page post-entry-29840'><div class='entry-content-wrapper clearfix'>\n<div class='flex_column_table av-equal-height-column-flextable -flextable' style='margin-top:20px; margin-bottom:0px; '><div class=\"flex_column av_three_fourth  flex_column_table_cell av-equal-height-column av-align-top first  avia-builder-el-1  el_before_av_one_fourth  avia-builder-el-first  \" style='padding:0px 0px 0px 0px ; border-radius:0px; '><section class=\"av_textblock_section \"  itemscope=\"itemscope\" itemtype=\"https:\/\/schema.org\/BlogPosting\" itemprop=\"blogPost\" ><div class='avia_textblock  '   itemprop=\"text\" ><h1>Where Circuit Simulation Model Files Come From<\/h1>\n<p style=\"box-sizing: border-box; margin: 0px 0px 20px; line-height: 24px; letter-spacing: normal; color: #0a0a0a; font-family: 'Open Sans', sans-serif; font-size: 14px; font-style: normal; font-variant-ligatures: normal; font-variant-caps: normal; font-weight: 400; orphans: 2; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; -webkit-text-stroke-width: 0px; background-color: #ffffff; text-decoration-style: initial; text-decoration-color: initial;\">*** This article by\u00a0<a href=\"https:\/\/semiwiki.com\/forum\/index.php?members\/daniel-payne.57\/\" target=\"_blank\" rel=\"noreferrer noopener\">Daniel Payne<\/a>\u00a0was first published on\u00a0<a href=\"https:\/\/semiwiki.com\/eda\/silvaco\/7993-where-circuit-simulation-model-files-come-from\/\" target=\"_blank\" rel=\"noreferrer noopener\">SemiWiki.com<\/a>\u00a0***<\/p>\n<p style=\"box-sizing: border-box; margin: 0px 0px 20px; line-height: 24px; letter-spacing: normal; color: #0a0a0a; font-family: 'Open Sans', sans-serif; font-size: 14px; font-style: normal; font-variant-ligatures: normal; font-variant-caps: normal; font-weight: 400; orphans: 2; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; -webkit-text-stroke-width: 0px; background-color: #ffffff; text-decoration-style: initial; text-decoration-color: initial;\">I started out my engineering career by doing transistor-level circuit design and we used a proprietary SPICE circuit simulator. One thing that I quickly realized was that the accuracy of my circuit simulations depended entirely on the model files and parasitics. Here we are 40 years later and the accuracy of SPICE circuit simulations still depend on the model files and parasitics, but with the added task of using 3D field solvers to get accurate parasitic values, and even the use of 3D TCAD tools to model the complex physics of nm IC designs using FinFET transistors.<\/p>\n<p style=\"box-sizing: border-box; margin: 0px 0px 20px; line-height: 24px; letter-spacing: normal; color: #0a0a0a; font-family: 'Open Sans', sans-serif; font-size: 14px; font-style: normal; font-variant-ligatures: normal; font-variant-caps: normal; font-weight: 400; orphans: 2; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; -webkit-text-stroke-width: 0px; background-color: #ffffff; text-decoration-style: initial; text-decoration-color: initial;\">Foundries and IDMs both need a proven and accurate flow from TCAD to SPICE simulation for accurate FinFET behavior that match silicon measurements. This blog will consider such a flow using tools from\u00a0<strong>Silvaco<\/strong>\u00a0like\u00a0<strong>DeckBuild<\/strong>\u00a0or the\u00a0<strong>Virtual Wafer Fab<\/strong>\u00a0(VWF). I will start with an example circuit of a 9-stage ring oscillator using a FinFET technology with 20nm gate lengths:<\/p>\n<p><img loading=\"lazy\" decoding=\"async\" class=\"aligncenter wp-image-8545 size-full\" src=\"\/wp-content\/uploads\/2020\/04\/Blog21.jpg\" alt=\"\" width=\"532\" height=\"395\" srcset=\"https:\/\/silvaco.com\/wp-content\/uploads\/2020\/04\/Blog21.jpg 532w, https:\/\/silvaco.com\/wp-content\/uploads\/2020\/04\/Blog21-300x223.jpg 300w, https:\/\/silvaco.com\/wp-content\/uploads\/2020\/04\/Blog21-43x32.jpg 43w, https:\/\/silvaco.com\/wp-content\/uploads\/2020\/04\/Blog21-63x47.jpg 63w, https:\/\/silvaco.com\/wp-content\/uploads\/2020\/04\/Blog21-48x36.jpg 48w\" sizes=\"(max-width: 532px) 100vw, 532px\" \/><\/p>\n<p style=\"box-sizing: border-box; margin: 0px 0px 20px; line-height: 24px; letter-spacing: normal; color: #0a0a0a; font-family: 'Open Sans', sans-serif; font-size: 14px; font-style: normal; font-variant-ligatures: normal; font-variant-caps: normal; font-weight: 400; orphans: 2; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; -webkit-text-stroke-width: 0px; background-color: #ffffff; text-decoration-style: initial; text-decoration-color: initial;\">The next step is to create an annotated layout that identifies active devices (FinFET transistors) and the interconnect between the devices:<\/p>\n<p><img loading=\"lazy\" decoding=\"async\" class=\"aligncenter wp-image-8546 size-full\" src=\"\/wp-content\/uploads\/2020\/04\/Blog22.jpg\" alt=\"\" width=\"550\" height=\"335\" srcset=\"https:\/\/silvaco.com\/wp-content\/uploads\/2020\/04\/Blog22.jpg 550w, https:\/\/silvaco.com\/wp-content\/uploads\/2020\/04\/Blog22-300x183.jpg 300w, https:\/\/silvaco.com\/wp-content\/uploads\/2020\/04\/Blog22-43x26.jpg 43w, https:\/\/silvaco.com\/wp-content\/uploads\/2020\/04\/Blog22-63x38.jpg 63w, https:\/\/silvaco.com\/wp-content\/uploads\/2020\/04\/Blog22-48x29.jpg 48w\" sizes=\"(max-width: 550px) 100vw, 550px\" \/><\/p>\n<p style=\"box-sizing: border-box; margin: 0px 0px 20px; line-height: 24px; letter-spacing: normal; color: #0a0a0a; font-family: 'Open Sans', sans-serif; font-size: 14px; font-style: normal; font-variant-ligatures: normal; font-variant-caps: normal; font-weight: 400; orphans: 2; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; -webkit-text-stroke-width: 0px; background-color: #ffffff; text-decoration-style: initial; text-decoration-color: initial;\">The initial IC layout is performed on a 2D representation, so the TCAD tool takes this 2D info as a starting point in doing a 3D process simulation where we get to choose process parameters like:<\/p>\n<ul style=\"box-sizing: border-box; margin-top: 0px; margin-bottom: 1rem; color: #0a0a0a; font-family: 'Open Sans', sans-serif; font-size: 14px; font-style: normal; font-variant-ligatures: normal; font-variant-caps: normal; font-weight: 400; letter-spacing: normal; orphans: 2; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; -webkit-text-stroke-width: 0px; background-color: #ffffff; text-decoration-style: initial; text-decoration-color: initial;\">\n<li>Fin height<\/li>\n<li>Equivalent gate oxide thickness<\/li>\n<li>Source-drain diffusion times<\/li>\n<\/ul>\n<p style=\"box-sizing: border-box; margin: 0px 0px 20px; line-height: 24px; letter-spacing: normal; color: #0a0a0a; font-family: 'Open Sans', sans-serif; font-size: 14px; font-style: normal; font-variant-ligatures: normal; font-variant-caps: normal; font-weight: 400; orphans: 2; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; -webkit-text-stroke-width: 0px; background-color: #ffffff; text-decoration-style: initial; text-decoration-color: initial;\">With just a handful of input parameters the process simulator then automates the device meshing and creates a 3D representation of a p-channel FinFET including the SiGe source-drain stressors for mobility enhancement:<\/p>\n<p><img loading=\"lazy\" decoding=\"async\" class=\"aligncenter wp-image-8547 size-full\" src=\"\/wp-content\/uploads\/2020\/04\/Blog23.jpg\" alt=\"\" width=\"360\" height=\"648\" srcset=\"https:\/\/silvaco.com\/wp-content\/uploads\/2020\/04\/Blog23.jpg 360w, https:\/\/silvaco.com\/wp-content\/uploads\/2020\/04\/Blog23-167x300.jpg 167w, https:\/\/silvaco.com\/wp-content\/uploads\/2020\/04\/Blog23-21x37.jpg 21w, https:\/\/silvaco.com\/wp-content\/uploads\/2020\/04\/Blog23-31x55.jpg 31w, https:\/\/silvaco.com\/wp-content\/uploads\/2020\/04\/Blog23-27x48.jpg 27w\" sizes=\"(max-width: 360px) 100vw, 360px\" \/><\/p>\n<p style=\"box-sizing: border-box; margin: 0px 0px 20px; line-height: 24px; letter-spacing: normal; color: #0a0a0a; font-family: 'Open Sans', sans-serif; font-size: 14px; font-style: normal; font-variant-ligatures: normal; font-variant-caps: normal; font-weight: 400; orphans: 2; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; -webkit-text-stroke-width: 0px; background-color: #ffffff; text-decoration-style: initial; text-decoration-color: initial;\">The 3D TCAD simulator\u00a0<strong>Victory<\/strong>\u00a0will automatically create the SPICE model files based on the p-channel and n-channel physical and electrical characteristics. Process engineers can iterate and investigate how different process parameters, strain and layout effects impact circuit performance (aka Design Technology Co-optimization).<\/p>\n<p style=\"box-sizing: border-box; margin: 0px 0px 20px; line-height: 24px; letter-spacing: normal; color: #0a0a0a; font-family: 'Open Sans', sans-serif; font-size: 14px; font-style: normal; font-variant-ligatures: normal; font-variant-caps: normal; font-weight: 400; orphans: 2; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; -webkit-text-stroke-width: 0px; background-color: #ffffff; text-decoration-style: initial; text-decoration-color: initial;\">With a transistor model, you can then visualize the I-V curves for p and n transistors:<\/p>\n<p><img loading=\"lazy\" decoding=\"async\" class=\"aligncenter wp-image-8535 size-full\" src=\"\/wp-content\/uploads\/2020\/04\/Blog24.jpg\" alt=\"\" width=\"550\" height=\"450\" srcset=\"https:\/\/silvaco.com\/wp-content\/uploads\/2020\/04\/Blog24.jpg 550w, https:\/\/silvaco.com\/wp-content\/uploads\/2020\/04\/Blog24-300x245.jpg 300w, https:\/\/silvaco.com\/wp-content\/uploads\/2020\/04\/Blog24-43x35.jpg 43w, https:\/\/silvaco.com\/wp-content\/uploads\/2020\/04\/Blog24-63x52.jpg 63w, https:\/\/silvaco.com\/wp-content\/uploads\/2020\/04\/Blog24-48x39.jpg 48w\" sizes=\"(max-width: 550px) 100vw, 550px\" \/><\/p>\n<p><img loading=\"lazy\" decoding=\"async\" class=\"aligncenter wp-image-8536 size-full\" src=\"\/wp-content\/uploads\/2020\/04\/Blog25.jpg\" alt=\"\" width=\"550\" height=\"423\" srcset=\"https:\/\/silvaco.com\/wp-content\/uploads\/2020\/04\/Blog25.jpg 550w, https:\/\/silvaco.com\/wp-content\/uploads\/2020\/04\/Blog25-300x231.jpg 300w, https:\/\/silvaco.com\/wp-content\/uploads\/2020\/04\/Blog25-43x33.jpg 43w, https:\/\/silvaco.com\/wp-content\/uploads\/2020\/04\/Blog25-63x48.jpg 63w, https:\/\/silvaco.com\/wp-content\/uploads\/2020\/04\/Blog25-48x37.jpg 48w\" sizes=\"(max-width: 550px) 100vw, 550px\" \/><\/p>\n<p style=\"box-sizing: border-box; margin: 0px 0px 20px; line-height: 24px; letter-spacing: normal; color: #0a0a0a; font-family: 'Open Sans', sans-serif; font-size: 14px; font-style: normal; font-variant-ligatures: normal; font-variant-caps: normal; font-weight: 400; orphans: 2; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; -webkit-text-stroke-width: 0px; background-color: #ffffff; text-decoration-style: initial; text-decoration-color: initial;\">When running device simulations the process engineer decides which device physics to include:<\/p>\n<ul style=\"box-sizing: border-box; margin-top: 0px; margin-bottom: 1rem; color: #0a0a0a; font-family: 'Open Sans', sans-serif; font-size: 14px; font-style: normal; font-variant-ligatures: normal; font-variant-caps: normal; font-weight: 400; letter-spacing: normal; orphans: 2; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; -webkit-text-stroke-width: 0px; background-color: #ffffff; text-decoration-style: initial; text-decoration-color: initial;\">\n<li>Standard model set<\/li>\n<li>Strain effects<\/li>\n<li>Gate tunneling<\/li>\n<li>Band to band tunneling<\/li>\n<li>User-defined effects<\/li>\n<\/ul>\n<p style=\"box-sizing: border-box; margin: 0px 0px 20px; line-height: 24px; letter-spacing: normal; color: #0a0a0a; font-family: 'Open Sans', sans-serif; font-size: 14px; font-style: normal; font-variant-ligatures: normal; font-variant-caps: normal; font-weight: 400; orphans: 2; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; -webkit-text-stroke-width: 0px; background-color: #ffffff; text-decoration-style: initial; text-decoration-color: initial;\">Finally, the BSIM-CMG models are created based upon these TCAD I-V curves and the 3D physics involved. In the 1970\u2019s we only had proprietary models and SPICE simulators, but today we have model standards like BSIM-CMG which is approved by the Compact Modeling Council.<\/p>\n<p style=\"box-sizing: border-box; margin: 0px 0px 20px; line-height: 24px; letter-spacing: normal; color: #0a0a0a; font-family: 'Open Sans', sans-serif; font-size: 14px; font-style: normal; font-variant-ligatures: normal; font-variant-caps: normal; font-weight: 400; orphans: 2; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; -webkit-text-stroke-width: 0px; background-color: #ffffff; text-decoration-style: initial; text-decoration-color: initial;\">You can customized how your model cards are created if needed by using the\u00a0<strong>Utmost-IV<\/strong>\u00a0GUI, but for this example a standard script was used without any tweaking. One quality control step is to check the difference between the original I-V curves and the generated SPICE model, look at how close these sets of curves are:<\/p>\n<p><img loading=\"lazy\" decoding=\"async\" class=\"aligncenter wp-image-8537 size-full\" src=\"\/wp-content\/uploads\/2020\/04\/Blog26.jpg\" alt=\"\" width=\"550\" height=\"431\" srcset=\"https:\/\/silvaco.com\/wp-content\/uploads\/2020\/04\/Blog26.jpg 550w, https:\/\/silvaco.com\/wp-content\/uploads\/2020\/04\/Blog26-300x235.jpg 300w, https:\/\/silvaco.com\/wp-content\/uploads\/2020\/04\/Blog26-43x34.jpg 43w, https:\/\/silvaco.com\/wp-content\/uploads\/2020\/04\/Blog26-63x49.jpg 63w, https:\/\/silvaco.com\/wp-content\/uploads\/2020\/04\/Blog26-48x38.jpg 48w\" sizes=\"(max-width: 550px) 100vw, 550px\" \/><\/p>\n<p><img loading=\"lazy\" decoding=\"async\" class=\"aligncenter wp-image-8538 size-full\" src=\"\/wp-content\/uploads\/2020\/04\/Blog27.jpg\" alt=\"\" width=\"550\" height=\"404\" srcset=\"https:\/\/silvaco.com\/wp-content\/uploads\/2020\/04\/Blog27.jpg 550w, https:\/\/silvaco.com\/wp-content\/uploads\/2020\/04\/Blog27-300x220.jpg 300w, https:\/\/silvaco.com\/wp-content\/uploads\/2020\/04\/Blog27-43x32.jpg 43w, https:\/\/silvaco.com\/wp-content\/uploads\/2020\/04\/Blog27-63x46.jpg 63w, https:\/\/silvaco.com\/wp-content\/uploads\/2020\/04\/Blog27-48x35.jpg 48w\" sizes=\"(max-width: 550px) 100vw, 550px\" \/><\/p>\n<p style=\"box-sizing: border-box; margin: 0px 0px 20px; line-height: 24px; letter-spacing: normal; color: #0a0a0a; font-family: 'Open Sans', sans-serif; font-size: 14px; font-style: normal; font-variant-ligatures: normal; font-variant-caps: normal; font-weight: 400; orphans: 2; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; -webkit-text-stroke-width: 0px; background-color: #ffffff; text-decoration-style: initial; text-decoration-color: initial;\">When I look at the TCAD curves versus SPICE model curves, the values are consistent. The\u00a0<strong>Utmost-IV<\/strong>\u00a0tool does have a full SPICE simulator that is used to fit the curves so closely, saving time for us and keeping the desired accuracy. So the transistors are well modeled in this tool flow and it\u2019s time to look at the interconnect between devices.<\/p>\n<p style=\"box-sizing: border-box; margin: 0px 0px 20px; line-height: 24px; letter-spacing: normal; color: #0a0a0a; font-family: 'Open Sans', sans-serif; font-size: 14px; font-style: normal; font-variant-ligatures: normal; font-variant-caps: normal; font-weight: 400; orphans: 2; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; -webkit-text-stroke-width: 0px; background-color: #ffffff; text-decoration-style: initial; text-decoration-color: initial;\">Just as the FinFET devices required 3D modeling, the interconnect between FinFET transistors also requires a 3D field solver,\u00a0<strong>Clever<\/strong>, to extract accurate resistance and capacitance values. The 3D Back End Of Line (<strong>BEOL<\/strong>) structure for the nine-stage inverter layout is shown below where Metal 2 is in Red, Metal 1 is Purple:<\/p>\n<p><img loading=\"lazy\" decoding=\"async\" class=\"aligncenter wp-image-8539 size-full\" src=\"\/wp-content\/uploads\/2020\/04\/Blog28.jpg\" alt=\"\" width=\"550\" height=\"456\" srcset=\"https:\/\/silvaco.com\/wp-content\/uploads\/2020\/04\/Blog28.jpg 550w, https:\/\/silvaco.com\/wp-content\/uploads\/2020\/04\/Blog28-300x249.jpg 300w, https:\/\/silvaco.com\/wp-content\/uploads\/2020\/04\/Blog28-43x37.jpg 43w, https:\/\/silvaco.com\/wp-content\/uploads\/2020\/04\/Blog28-63x52.jpg 63w, https:\/\/silvaco.com\/wp-content\/uploads\/2020\/04\/Blog28-48x40.jpg 48w\" sizes=\"(max-width: 550px) 100vw, 550px\" \/><\/p>\n<p style=\"box-sizing: border-box; margin: 0px 0px 20px; line-height: 24px; letter-spacing: normal; color: #0a0a0a; font-family: 'Open Sans', sans-serif; font-size: 14px; font-style: normal; font-variant-ligatures: normal; font-variant-caps: normal; font-weight: 400; orphans: 2; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; -webkit-text-stroke-width: 0px; background-color: #ffffff; text-decoration-style: initial; text-decoration-color: initial;\">This 3D field solver produces the SPICE netlist which has both FinFET transistors and RC interconnect values.<\/p>\n<p style=\"box-sizing: border-box; margin: 0px 0px 20px; line-height: 24px; letter-spacing: normal; color: #0a0a0a; font-family: 'Open Sans', sans-serif; font-size: 14px; font-style: normal; font-variant-ligatures: normal; font-variant-caps: normal; font-weight: 400; orphans: 2; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; -webkit-text-stroke-width: 0px; background-color: #ffffff; text-decoration-style: initial; text-decoration-color: initial;\">An engineer can even run a large Design Of Experiments (<strong>DOE<\/strong>) with the Virtual Wafer Fab tool and use the built-in statistical features to fit response surface models, relating input variables to predicted outputs.<\/p>\n<p style=\"box-sizing: border-box; margin: 0px 0px 20px; line-height: 24px; letter-spacing: normal; color: #0a0a0a; font-family: 'Open Sans', sans-serif; font-size: 14px; font-style: normal; font-variant-ligatures: normal; font-variant-caps: normal; font-weight: 400; orphans: 2; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; -webkit-text-stroke-width: 0px; background-color: #ffffff; text-decoration-style: initial; text-decoration-color: initial;\">Running the SPICE netlist in the\u00a0<strong>SmartSpice<\/strong>\u00a0circuit simulator shows that the 9 stage ring oscillator is functioning properly (left plot), and we know the average power consumption (right plot).<\/p>\n<p><img loading=\"lazy\" decoding=\"async\" class=\"aligncenter wp-image-8540 size-full\" src=\"\/wp-content\/uploads\/2020\/04\/Blog29.jpg\" alt=\"\" width=\"550\" height=\"223\" srcset=\"https:\/\/silvaco.com\/wp-content\/uploads\/2020\/04\/Blog29.jpg 550w, https:\/\/silvaco.com\/wp-content\/uploads\/2020\/04\/Blog29-300x122.jpg 300w, https:\/\/silvaco.com\/wp-content\/uploads\/2020\/04\/Blog29-43x17.jpg 43w, https:\/\/silvaco.com\/wp-content\/uploads\/2020\/04\/Blog29-63x26.jpg 63w, https:\/\/silvaco.com\/wp-content\/uploads\/2020\/04\/Blog29-48x19.jpg 48w\" sizes=\"(max-width: 550px) 100vw, 550px\" \/><\/p>\n<p><span style=\"color: #0a0a0a; font-family: 'Open Sans', sans-serif; font-size: 14px; font-style: normal; font-variant-ligatures: normal; font-variant-caps: normal; font-weight: 400; letter-spacing: normal; orphans: 2; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; -webkit-text-stroke-width: 0px; background-color: #ffffff; text-decoration-style: initial; text-decoration-color: initial; display: inline !important; float: none;\">This same TCAD to SPICE model file flow was also run on a\u00a0<\/span><strong style=\"box-sizing: border-box; font-weight: bold; color: #0a0a0a; font-family: 'Open Sans', sans-serif; font-size: 14px; font-style: normal; font-variant-ligatures: normal; font-variant-caps: normal; letter-spacing: normal; orphans: 2; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; -webkit-text-stroke-width: 0px; background-color: #ffffff; text-decoration-style: initial; text-decoration-color: initial;\">D-type Flip Flop<\/strong><span style=\"color: #0a0a0a; font-family: 'Open Sans', sans-serif; font-size: 14px; font-style: normal; font-variant-ligatures: normal; font-variant-caps: normal; font-weight: 400; letter-spacing: normal; orphans: 2; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; -webkit-text-stroke-width: 0px; background-color: #ffffff; text-decoration-style: initial; text-decoration-color: initial; display: inline !important; float: none;\"> from the Foundation IP<\/span><span style=\"color: #0a0a0a; font-family: 'Open Sans', sans-serif; font-size: 14px; font-style: normal; font-variant-ligatures: normal; font-variant-caps: normal; font-weight: 400; letter-spacing: normal; orphans: 2; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; -webkit-text-stroke-width: 0px; background-color: #ffffff; text-decoration-style: initial; text-decoration-color: initial; display: inline !important; float: none;\">\u00a0digital library, here\u2019s the 3D interconnect view:<\/span><\/p>\n<p><img loading=\"lazy\" decoding=\"async\" class=\"aligncenter wp-image-8541 size-full\" src=\"\/wp-content\/uploads\/2020\/04\/Blog30.jpg\" alt=\"\" width=\"550\" height=\"344\" srcset=\"https:\/\/silvaco.com\/wp-content\/uploads\/2020\/04\/Blog30.jpg 550w, https:\/\/silvaco.com\/wp-content\/uploads\/2020\/04\/Blog30-300x188.jpg 300w, https:\/\/silvaco.com\/wp-content\/uploads\/2020\/04\/Blog30-43x27.jpg 43w, https:\/\/silvaco.com\/wp-content\/uploads\/2020\/04\/Blog30-63x39.jpg 63w, https:\/\/silvaco.com\/wp-content\/uploads\/2020\/04\/Blog30-48x30.jpg 48w\" sizes=\"(max-width: 550px) 100vw, 550px\" \/><\/p>\n<p><span style=\"display: inline !important; float: none; background-color: #ffffff; color: #333333; cursor: text; font-family: Georgia,'Times New Roman','Bitstream Charter',Times,serif; font-size: 16px; font-style: normal; font-variant: normal; font-weight: 400; letter-spacing: normal; orphans: 2; text-align: left; text-decoration: none; text-indent: 0px; text-transform: none; -webkit-text-stroke-width: 0px; white-space: normal; word-spacing: 0px;\">All possible logic states are simulated with SmartSpice on the Flip Flop netlist using extracted parasitics:<\/span><\/p>\n<p><img loading=\"lazy\" decoding=\"async\" class=\"aligncenter wp-image-8542 size-full\" src=\"\/wp-content\/uploads\/2020\/04\/Blog31.jpg\" alt=\"\" width=\"550\" height=\"429\" srcset=\"https:\/\/silvaco.com\/wp-content\/uploads\/2020\/04\/Blog31.jpg 550w, https:\/\/silvaco.com\/wp-content\/uploads\/2020\/04\/Blog31-300x234.jpg 300w, https:\/\/silvaco.com\/wp-content\/uploads\/2020\/04\/Blog31-43x34.jpg 43w, https:\/\/silvaco.com\/wp-content\/uploads\/2020\/04\/Blog31-63x49.jpg 63w, https:\/\/silvaco.com\/wp-content\/uploads\/2020\/04\/Blog31-48x37.jpg 48w\" sizes=\"(max-width: 550px) 100vw, 550px\" \/><\/p>\n<p style=\"box-sizing: border-box; margin: 0px 0px 20px; line-height: 24px; letter-spacing: normal; color: #0a0a0a; font-family: 'Open Sans', sans-serif; font-size: 14px; font-style: normal; font-variant-ligatures: normal; font-variant-caps: normal; font-weight: 400; orphans: 2; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; -webkit-text-stroke-width: 0px; background-color: #ffffff; text-decoration-style: initial; text-decoration-color: initial;\">A CAD engineer could run many of these steps using the\u00a0<strong>DeckBuild<\/strong>\u00a0environment, or for further automation you should consider using the\u00a0<strong>Virtual Wafer Fab <\/strong>tool instead. An example of using VWF is for a Design Of Experiments where a virtual split lot tree is built and run across many computers, where the final results are fitted to a\u00a0<strong>Response Surface Model<\/strong>\u00a0(RSM):<\/p>\n<p><img loading=\"lazy\" decoding=\"async\" class=\"aligncenter wp-image-8543 size-full\" src=\"\/wp-content\/uploads\/2020\/04\/Blog32.jpg\" alt=\"\" width=\"550\" height=\"291\" srcset=\"https:\/\/silvaco.com\/wp-content\/uploads\/2020\/04\/Blog32.jpg 550w, https:\/\/silvaco.com\/wp-content\/uploads\/2020\/04\/Blog32-300x159.jpg 300w, https:\/\/silvaco.com\/wp-content\/uploads\/2020\/04\/Blog32-43x23.jpg 43w, https:\/\/silvaco.com\/wp-content\/uploads\/2020\/04\/Blog32-63x33.jpg 63w, https:\/\/silvaco.com\/wp-content\/uploads\/2020\/04\/Blog32-48x25.jpg 48w\" sizes=\"(max-width: 550px) 100vw, 550px\" \/><\/p>\n<p><img loading=\"lazy\" decoding=\"async\" class=\"aligncenter wp-image-8544 size-full\" src=\"\/wp-content\/uploads\/2020\/04\/Blog33.jpg\" alt=\"\" width=\"550\" height=\"397\" srcset=\"https:\/\/silvaco.com\/wp-content\/uploads\/2020\/04\/Blog33.jpg 550w, https:\/\/silvaco.com\/wp-content\/uploads\/2020\/04\/Blog33-300x217.jpg 300w, https:\/\/silvaco.com\/wp-content\/uploads\/2020\/04\/Blog33-43x31.jpg 43w, https:\/\/silvaco.com\/wp-content\/uploads\/2020\/04\/Blog33-63x45.jpg 63w, https:\/\/silvaco.com\/wp-content\/uploads\/2020\/04\/Blog33-48x35.jpg 48w\" sizes=\"(max-width: 550px) 100vw, 550px\" \/><\/p>\n<p style=\"box-sizing: border-box; margin: 0px 0px 20px; line-height: 24px; letter-spacing: normal; color: #0a0a0a; font-family: 'Open Sans', sans-serif; font-size: 14px; font-style: normal; font-variant-ligatures: normal; font-variant-caps: normal; font-weight: 400; orphans: 2; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; -webkit-text-stroke-width: 0px; background-color: #ffffff; text-decoration-style: initial; text-decoration-color: initial;\">One insight from the RSM is that the maximum frequency is inversely proportional to the metal line width, to this particular circuit is parasitic capacitance limited, instead of resistance limited. Now the circuit designer knows how to better make trade-offs in reaching the requirements.<\/p>\n<p style=\"box-sizing: border-box; margin: 0px 0px 20px; line-height: 24px; letter-spacing: normal; color: #0a0a0a; font-family: 'Open Sans', sans-serif; font-size: 14px; font-style: normal; font-variant-ligatures: normal; font-variant-caps: normal; font-weight: 400; orphans: 2; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; -webkit-text-stroke-width: 0px; background-color: #ffffff; text-decoration-style: initial; text-decoration-color: initial;\"><strong>Summary<br \/>\n<\/strong>I\u2019ve laid out the steps used by process engineers and CAD engineers to create SPICE model files:<\/p>\n<ul style=\"box-sizing: border-box; margin-top: 0px; margin-bottom: 1rem; color: #0a0a0a; font-family: 'Open Sans', sans-serif; font-size: 14px; font-style: normal; font-variant-ligatures: normal; font-variant-caps: normal; font-weight: 400; letter-spacing: normal; orphans: 2; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; -webkit-text-stroke-width: 0px; background-color: #ffffff; text-decoration-style: initial; text-decoration-color: initial;\">\n<li>3D TCAD simulation (Victory)<\/li>\n<li>SPICE model parameter extraction (Utmost IV)<\/li>\n<li>3D netlist extraction (Clever)<\/li>\n<li>SPICE simulation (SmartSpice)<\/li>\n<\/ul>\n<p style=\"box-sizing: border-box; margin: 0px 0px 20px; line-height: 24px; letter-spacing: normal; color: #0a0a0a; font-family: 'Open Sans', sans-serif; font-size: 14px; font-style: normal; font-variant-ligatures: normal; font-variant-caps: normal; font-weight: 400; orphans: 2; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; -webkit-text-stroke-width: 0px; background-color: #ffffff; text-decoration-style: initial; text-decoration-color: initial;\">Silvaco has all four tools needed in this tool flow and they also added plenty of automation to save your team precious time (VWF) for performing Design Of Experiments. For more details read the recent article in Silvaco\u2019s\u00a0<a href=\"https:\/\/silvaco.com\/ja\/simulation-standard-ja\/process-variation-alignment-and-beol-effects-on-circuit-level-performance\/\" target=\"_blank\" rel=\"noreferrer noopener\" aria-label=\" (opens in a new tab)\"><strong>Simulation Standard<\/strong><\/a>\u00a0online.<\/p>\n<p style=\"box-sizing: border-box; margin: 0px 0px 20px; line-height: 24px; letter-spacing: normal; color: #0a0a0a; font-family: 'Open Sans', sans-serif; font-size: 14px; font-style: normal; font-variant-ligatures: normal; font-variant-caps: normal; font-weight: 400; orphans: 2; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 2; word-spacing: 0px; -webkit-text-stroke-width: 0px; background-color: #ffffff; text-decoration-style: initial; text-decoration-color: initial;\">To read the rest of this blog continue to\u00a0<a href=\"https:\/\/semiwiki.com\/eda\/silvaco\/7993-where-circuit-simulation-model-files-come-from\/\" target=\"_blank\" rel=\"noreferrer noopener\">Where Circuit Simulation Model Files Come From on SemiWiki.com<\/a>.<\/p>\n<\/div><\/section><\/div><div class='av-flex-placeholder'><\/div><div class=\"flex_column av_one_fourth  flex_column_table_cell av-equal-height-column av-align-top av-zero-column-padding   avia-builder-el-3  el_after_av_three_fourth  avia-builder-el-last  \" style='border-radius:0px; '><div  class='avia-builder-widget-area clearfix  avia-builder-el-4  avia-builder-el-no-sibling '><div id=\"nav_menu-27\" class=\"widget clearfix widget_nav_menu\"><div class=\"menu-blog-side-menu-japanese-container\"><ul id=\"menu-blog-side-menu-japanese\" class=\"menu\"><li id=\"menu-item-26248\" class=\"menu-item menu-item-type-post_type menu-item-object-page menu-item-has-children menu-item-26248\"><a href=\"https:\/\/silvaco.com\/ja\/blog\/\">Blogs<\/a>\n<ul class=\"sub-menu\">\n\t<li id=\"menu-item-26249\" class=\"menu-item menu-item-type-post_type menu-item-object-page menu-item-26249\"><a href=\"https:\/\/silvaco.com\/ja\/corporate\/blogs\/analog-custom-ic-design-blogs\/\">Analog Custom IC Design Blogs<\/a><\/li>\n\t<li id=\"menu-item-26250\" class=\"menu-item menu-item-type-post_type menu-item-object-page menu-item-26250\"><a href=\"https:\/\/silvaco.com\/ja\/blogs\/design-ip\/\">Design IP Blogs<\/a><\/li>\n\t<li id=\"menu-item-26251\" class=\"menu-item menu-item-type-post_type menu-item-object-page menu-item-26251\"><a href=\"https:\/\/silvaco.com\/ja\/meet-silvaco-blogs\/\">Meet Silvaco Blogs<\/a><\/li>\n\t<li id=\"menu-item-26252\" class=\"menu-item menu-item-type-post_type menu-item-object-page menu-item-26252\"><a href=\"https:\/\/silvaco.com\/ja\/tcad-blogs-2\/\">TCAD Blogs<\/a><\/li>\n<\/ul>\n<\/li>\n<\/ul><\/div><\/div><\/div><\/div><\/div><!--close column table wrapper. Autoclose: 1 -->\n","protected":false},"excerpt":{"rendered":"<p>I started out my engineering career by doing transistor-level circuit design and we used a proprietary SPICE circuit simulator. One thing that I quickly realized was that the accuracy of my circuit simulations depended entirely on the model files and parasitics. Here we are 40 years later and the accuracy of SPICE circuit simulations still depend on the model files and parasitics, but with the added task of using 3D field solvers to get accurate parasitic values, and even the use of 3D TCAD tools to model the complex physics of nm IC designs using FinFET transistors. <\/p>\n","protected":false},"author":5,"featured_media":20264,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[7623],"tags":[],"yoast_head":"<!-- This site is optimized with the Yoast SEO Premium plugin v24.0 (Yoast SEO v24.0) - https:\/\/yoast.com\/wordpress\/plugins\/seo\/ -->\n<title>Where Circuit Simulation Model Files Come From - \u30b7\u30eb\u30d0\u30b3\u30fb\u30b8\u30e3\u30d1\u30f3 : Silvaco Japan<\/title>\n<meta name=\"description\" content=\"Where Circuit Simulation Model Files Come From\" \/>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link rel=\"canonical\" href=\"https:\/\/silvaco.com\/ja\/blog\/where-circuit-simulation-model-files-come-from\/\" \/>\n<meta property=\"og:locale\" content=\"ja_JP\" \/>\n<meta property=\"og:type\" content=\"article\" \/>\n<meta property=\"og:title\" content=\"Where Circuit Simulation Model Files Come From\" \/>\n<meta property=\"og:description\" content=\"Where Circuit Simulation Model Files Come From\" \/>\n<meta property=\"og:url\" content=\"https:\/\/silvaco.com\/ja\/blog\/where-circuit-simulation-model-files-come-from\/\" \/>\n<meta property=\"og:site_name\" content=\"\u30b7\u30eb\u30d0\u30b3\u30fb\u30b8\u30e3\u30d1\u30f3 : Silvaco Japan\" \/>\n<meta property=\"article:publisher\" content=\"https:\/\/www.facebook.com\/SilvacoSoftware\/\" \/>\n<meta property=\"article:published_time\" content=\"2019-08-29T16:54:31+00:00\" \/>\n<meta property=\"article:modified_time\" content=\"2021-08-05T05:40:55+00:00\" \/>\n<meta property=\"og:image\" content=\"https:\/\/silvaco.com\/wp-content\/uploads\/2020\/04\/tcad_process_device-11.jpg\" \/>\n\t<meta property=\"og:image:width\" content=\"500\" \/>\n\t<meta property=\"og:image:height\" content=\"500\" \/>\n\t<meta property=\"og:image:type\" content=\"image\/jpeg\" \/>\n<meta name=\"author\" content=\"Ingrid Schwarz\" \/>\n<meta name=\"twitter:card\" content=\"summary_large_image\" \/>\n<meta name=\"twitter:creator\" content=\"@SilvacoSoftware\" \/>\n<meta name=\"twitter:site\" content=\"@SilvacoSoftware\" \/>\n<meta name=\"twitter:label1\" content=\"\u57f7\u7b46\u8005\" \/>\n\t<meta name=\"twitter:data1\" content=\"Ingrid Schwarz\" \/>\n\t<meta name=\"twitter:label2\" content=\"\u63a8\u5b9a\u8aad\u307f\u53d6\u308a\u6642\u9593\" \/>\n\t<meta name=\"twitter:data2\" content=\"7\u5206\" \/>\n<script type=\"application\/ld+json\" class=\"yoast-schema-graph\">{\"@context\":\"https:\/\/schema.org\",\"@graph\":[{\"@type\":\"WebPage\",\"@id\":\"https:\/\/silvaco.com\/ja\/blog\/where-circuit-simulation-model-files-come-from\/\",\"url\":\"https:\/\/silvaco.com\/ja\/blog\/where-circuit-simulation-model-files-come-from\/\",\"name\":\"Where Circuit Simulation Model Files Come From - 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