{"id":29834,"date":"2020-01-07T15:26:01","date_gmt":"2020-01-07T15:26:01","guid":{"rendered":"https:\/\/silvaco.com\/uncategorized\/for-next-generation-nanowires-simulation-from-atoms-to-spice\/"},"modified":"2021-08-04T22:30:19","modified_gmt":"2021-08-05T05:30:19","slug":"for-next-generation-nanowires-simulation-from-atoms-to-spice","status":"publish","type":"post","link":"https:\/\/silvaco.com\/ja\/blog\/for-next-generation-nanowires-simulation-from-atoms-to-spice\/","title":{"rendered":"For Next Generation Nanowires, Simulation from Atoms to SPICE"},"content":{"rendered":"
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For Next Generation Nanowires, Simulation from Atoms to SPICE<\/h1>\n
As process nodes continue to shrink, the requirement for additional physics-based simulation is gradually creeping into each stage of the design process. By way of illustration, Technology Computer Aided Design (TCAD) simulations are becoming more atomistic in nature, SPICE models are becoming process aware to take account of localized strain effects, and back or middle end of line (BEOL or MEOL) parasitics are moving from exclusively two-dimensional (2D) rule-based solutions to full 3D structure field solvers for numerous critical sections of the layout.<\/span><\/div>\n
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With this extra requirement for additional physics for all stages of the design flow in mind, we must have a single design interactive environment to flow seamlessly from 3D process and device physics based TCAD, to final SPICE circuit simulation including SPICE model parameter extraction from the TCAD simulations. The modularity of the flow also allows entire sections of the flow to be left out if not required. For example, if SPICE model cards are sufficiently accurate, the designer can omit the TCAD sections of the flow and concentrate on design optimization on circuit performance.<\/p>\n

Here, a 3D atomistic to SPICE circuit simulation flow is demonstrated. It allows investigation of impact different variables of interest can have on the final circuit performance. Aspects such as process parameters, SPICE model fitting sequence, and changes in circuit configuration, can all be investigated through a single design environment. The tool flow sequence and user choices for each step are outlined in this article. The general DTCO flow is illustrated in Fig. 1.<\/p>\n

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Figure 1. Complete process flow from Atomistic simulation to SPICE modeling.<\/p><\/div>
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Figure2. Atomistic representation of silicon nanowire FET with 7nm channel, 2nm width and 2nm thickness.<\/p><\/div>\n<\/div>\n

To read the rest of this\u00a0<\/span>Simulation Standard\u00a0article go to\u00a0<\/span>Next Generation CMOS Nanowire: From Atoms to Circuit Simulation<\/a>.<\/span><\/p>\n<\/div><\/section><\/div>

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