{"id":29666,"date":"1999-06-01T17:46:52","date_gmt":"1999-06-01T17:46:52","guid":{"rendered":"https:\/\/silvaco.com\/uncategorized\/maverick-hierarchcal-full-chip-extractor-recent-significant-advances\/"},"modified":"2021-07-08T18:45:47","modified_gmt":"2021-07-09T01:45:47","slug":"maverick-hierarchcal-full-chip-extractor-recent-significant-advances","status":"publish","type":"post","link":"https:\/\/silvaco.com\/ja\/simulation-standard\/maverick-hierarchcal-full-chip-extractor-recent-significant-advances\/","title":{"rendered":"Maverick- Hierarchcal Full-Chip Extractor Recent Significant Advances"},"content":{"rendered":"
\n

Maverick<\/i>– Hierarchcal Full-Chip Extractor Recent Significant Advances<\/h1>\n

Introduction<\/p>\n

Maverick<\/i><\/b>\u00a0is a sophisticated full chip hierarchical netlist extractor [1]. It augments the existing\u00a0CELEBRITY<\/i><\/b>\u00a0framework which includes state-of-the-art software for VLSI layout editing, hierarchical design rule checking and layout versus schematic comparison. The latest release of\u00a0Maverick<\/i><\/b>\u00a0is equipped with many new interface features, including the ability to search for a net by name, and new engine upgrades, such as extraction of parameters of active devices. A new numerical procedure has been developed for resistance extraction of complex geometrical shapes.<\/p>\n

Parameter Extraction<\/p>\n

An important feature of any netlist extractor is the ability to accurately report geometrical active device parameters to the netlist.<\/p>\n

For MOS technology,\u00a0Maverick<\/i><\/b>\u00a0provides channel length (L<\/i>), channel width (W), drain diffusion area (AD<\/i>), source diffusion area (AS<\/i>), perimeter of the drain junction including the channel edge (PD<\/i>), perimeter of the source junction including the channel edge (PS<\/i>).<\/p>\n

For diodes, extraction is performed for the area of the diode (AREA<\/i>) and perimeter of junction (PJ<\/i>).<\/p>\n

For capacitors,\u00a0Maverick<\/i><\/b>\u00a0reports the capacitance combining inputs from the technology file with extracted geometries. To obtain the capacitance the technology file must include two technology constants: area capacitance (AreaAttr<\/i>\u00a0in aF\/?m2<\/sup>) and perimeter capacitance per unit length (PerimAttr<\/i>\u00a0in aF\/?m). These are supplied together with both layer names for the capacitor. A typical technology file input might be:<\/p>\n

\n

Capacitance<\/span><\/p>\n

\n

{<\/span><\/p>\n

Layer1 = “Pin1”<\/span><\/p>\n

Layer2 = “Pin2”<\/span><\/p>\n

AreaAttr = 60<\/span><\/p>\n

PerimAttr = 90<\/span><\/p>\n

}<\/span><\/p>\n<\/blockquote>\n<\/blockquote>\n<\/div><\/section><\/div>

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