{"id":29576,"date":"2000-07-01T21:00:27","date_gmt":"2000-07-01T21:00:27","guid":{"rendered":"https:\/\/silvaco.com\/uncategorized\/ufsoi-process-based-compact-soi-mosfet-models\/"},"modified":"2021-07-08T18:42:54","modified_gmt":"2021-07-09T01:42:54","slug":"ufsoi-process-based-compact-soi-mosfet-models","status":"publish","type":"post","link":"https:\/\/silvaco.com\/ja\/simulation-standard\/ufsoi-process-based-compact-soi-mosfet-models\/","title":{"rendered":"UFSOI: Process-Based Compact SOI MOSFET Models"},"content":{"rendered":"
\n

UFSOI: Process-Based Compact SOI MOSFET Models<\/h1>\n

Introduction<\/h3>\n

SOI technology appears now to have become an advantageous, viable option for low-voltage and high-performance CMOS integrated circuits in digital, analog, and mixed-signal applications. The thin-film nature of the SOI MOSFET, however, can underlie physical mechanisms that complicate circuit simulation and portend equivocation in design. For example, floating-body (FB) effects [1], which in fact are obtained even in body-tied devices due to unavoidable high resistance [2], render empirical compact models like those used for designing bulk-Si CMOS circuits inadequate for reliable SOI circuit simulation. Furthermore, such models cannot be easily calibrated using common parameter-optimization techniques because of ambiguous data acquisition implied by SOI device self-heating in DC measurements and\/or FB charge dynamics in pulse measurements designed to avoid self-heating; such optimization, because of the complex body charging dynamics, does not and cannot cover the large range of operational conditions that obtain in actual SOI CMOS circuits. Consequently, Silvaco has incorporated the physical process-based UFSOI MOSFET models [3] into\u00a0SmartSpice\u00a0and\u00a0Utmost.<\/p>\n<\/div><\/section><\/div>

<\/div>