{"id":29375,"date":"2003-07-01T21:27:56","date_gmt":"2003-07-01T21:27:56","guid":{"rendered":"https:\/\/silvaco.com\/uncategorized\/behavioral-modeling-of-pll-using-verilog-a-with-smartspice\/"},"modified":"2026-10-15T14:26:45","modified_gmt":"2026-10-15T21:26:45","slug":"behavioral-modeling-of-pll-using-verilog-a-with-smartspice","status":"publish","type":"post","link":"https:\/\/silvaco.com\/ja\/simulation-standard\/behavioral-modeling-of-pll-using-verilog-a-with-smartspice\/","title":{"rendered":"Behavioral Modeling of PLL Using Verilog-A with SmartSpice"},"content":{"rendered":"

Behavioral Modeling of PLL Using Verilog-A with SmartSpice<\/h1>\n

Introduction<\/h3>\n

In this article, we describe practical behavioral modeling for highly non-linear circuits using Verilog-A, which is analog extension of Verilog-AMS. At first, we describe behavioral modeling techniques for phase\/frequency detectors (PFD) and voltage-controlled oscillators (VCO) those are essential part of phase-locked loop systems shown in Figure.1. Model parameter extraction techniques are described and demonstrated later. Finally, these models are simulated with SmartSpice and verified against the results of transistor circuit simulations.<\/p>\n

\"\"<\/p>\n

Download Simulation Standard<\/a><\/p>\n","protected":false},"excerpt":{"rendered":"

In this article, we describe practical behavioral modeling for highly non-linear circuits using Verilog-A, which is analog extension of Verilog-AMS. At first, we describe behavioral modeling techniques for phase\/frequency detectors (PFD) and voltage-controlled oscillators (VCO) those are essential part of phase-locked loop systems shown in Figure.1. Model parameter extraction techniques are described and demonstrated later. Finally, these models are simulated with SmartSpice and verified against the results of transistor circuit simulations.<\/p>\n","protected":false},"author":12,"featured_media":21986,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"inline_featured_image":false,"footnotes":""},"categories":[7570],"tags":[],"class_list":["post-29375","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-simulation-standard","entry","has-media"],"yoast_head":"\nBehavioral Modeling of PLL Using Verilog-A with SmartSpice - Silvaco<\/title>\n<meta name=\"description\" content=\"Behavioral Modeling of PLL Using Verilog-A with SmartSpice\" \/>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link rel=\"canonical\" href=\"https:\/\/silvaco.com\/ja\/simulation-standard\/behavioral-modeling-of-pll-using-verilog-a-with-smartspice\/\" \/>\n<meta property=\"og:locale\" content=\"ja_JP\" \/>\n<meta property=\"og:type\" content=\"article\" \/>\n<meta property=\"og:title\" content=\"Behavioral Modeling of PLL Using Verilog-A with SmartSpice\" \/>\n<meta property=\"og:description\" content=\"Behavioral Modeling of PLL Using Verilog-A with SmartSpice\" \/>\n<meta property=\"og:url\" content=\"https:\/\/silvaco.com\/ja\/simulation-standard\/behavioral-modeling-of-pll-using-verilog-a-with-smartspice\/\" \/>\n<meta property=\"og:site_name\" content=\"Silvaco\" \/>\n<meta property=\"article:publisher\" content=\"https:\/\/www.facebook.com\/SilvacoSoftware\/\" \/>\n<meta property=\"article:published_time\" content=\"2003-07-01T21:27:56+00:00\" \/>\n<meta property=\"article:modified_time\" content=\"2026-10-15T21:26:45+00:00\" \/>\n<meta property=\"og:image\" content=\"https:\/\/silvaco.com\/wp-content\/uploads\/simulationstandard\/simstd_jul_2003_a2.jpg\" \/>\n\t<meta property=\"og:image:width\" content=\"1344\" \/>\n\t<meta property=\"og:image:height\" content=\"1669\" \/>\n\t<meta property=\"og:image:type\" content=\"image\/jpeg\" \/>\n<meta name=\"author\" content=\"Casey Molver\" \/>\n<meta name=\"twitter:card\" content=\"summary_large_image\" \/>\n<meta name=\"twitter:creator\" content=\"@SilvacoSoftware\" \/>\n<meta name=\"twitter:site\" content=\"@SilvacoSoftware\" \/>\n<meta name=\"twitter:label1\" content=\"\u57f7\u7b46\u8005\" \/>\n\t<meta name=\"twitter:data1\" content=\"Casey Molver\" \/>\n<script type=\"application\/ld+json\" class=\"yoast-schema-graph\">{\"@context\":\"https:\\\/\\\/schema.org\",\"@graph\":[{\"@type\":\"Article\",\"@id\":\"https:\\\/\\\/silvaco.com\\\/ja\\\/simulation-standard\\\/behavioral-modeling-of-pll-using-verilog-a-with-smartspice\\\/#article\",\"isPartOf\":{\"@id\":\"https:\\\/\\\/silvaco.com\\\/ja\\\/simulation-standard\\\/behavioral-modeling-of-pll-using-verilog-a-with-smartspice\\\/\"},\"author\":{\"name\":\"Casey Molver\",\"@id\":\"https:\\\/\\\/silvaco.com\\\/ja\\\/#\\\/schema\\\/person\\\/2763eb741ca5ac04477fdff50ed84c80\"},\"headline\":\"Behavioral Modeling of PLL Using Verilog-A with SmartSpice\",\"datePublished\":\"2003-07-01T21:27:56+00:00\",\"dateModified\":\"2026-10-15T21:26:45+00:00\",\"mainEntityOfPage\":{\"@id\":\"https:\\\/\\\/silvaco.com\\\/ja\\\/simulation-standard\\\/behavioral-modeling-of-pll-using-verilog-a-with-smartspice\\\/\"},\"wordCount\":92,\"image\":{\"@id\":\"https:\\\/\\\/silvaco.com\\\/ja\\\/simulation-standard\\\/behavioral-modeling-of-pll-using-verilog-a-with-smartspice\\\/#primaryimage\"},\"thumbnailUrl\":\"https:\\\/\\\/silvaco.com\\\/wp-content\\\/uploads\\\/simulationstandard\\\/simstd_jul_2003_a2.jpg\",\"articleSection\":[\"Simulation Standard\"],\"inLanguage\":\"ja\"},{\"@type\":\"WebPage\",\"@id\":\"https:\\\/\\\/silvaco.com\\\/ja\\\/simulation-standard\\\/behavioral-modeling-of-pll-using-verilog-a-with-smartspice\\\/\",\"url\":\"https:\\\/\\\/silvaco.com\\\/ja\\\/simulation-standard\\\/behavioral-modeling-of-pll-using-verilog-a-with-smartspice\\\/\",\"name\":\"Behavioral Modeling of PLL Using Verilog-A with SmartSpice - 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