{"id":29267,"date":"2004-07-01T00:10:37","date_gmt":"2004-07-01T00:10:37","guid":{"rendered":"https:\/\/silvaco.com\/uncategorized\/silvacos-rfic-design-suite\/"},"modified":"2021-07-08T18:29:40","modified_gmt":"2021-07-09T01:29:40","slug":"silvacos-rfic-design-suite","status":"publish","type":"post","link":"https:\/\/silvaco.com\/ja\/simulation-standard\/silvacos-rfic-design-suite\/","title":{"rendered":"Silvaco\u2019s RFIC Design Suite"},"content":{"rendered":"
\n

Silvaco\u2019s RFIC Design Suite<\/h1>\n

Introduction<\/strong><\/p>\n

This article focuses on the use of Silvaco\u2019s RFIC Design Suite including PDK,\u00a0SmartSpice-RF<\/strong><\/em>, and\u00a0Gateway<\/em><\/strong>.<\/p>\n

Silvaco Process Design Kits (PDKs) have been developed to help start the analog and mixed signal design cycles. The design kit supplies you with all the foundry process specific models, symbols, simulation setup for the Silvaco set of design tools.<\/p>\n

SmartSpice-RF<\/strong><\/em>\u00a0Harmonic Balance based Simulator provides a complete set of steady-state analyses and measurements to design GHz range RF wireless application ICs. It accurately and efficiently simulates noise, gain compression, harmonic distortion, oscillator phase noise, and intermodulation products in non-linear circuits using SPICE netlists.<\/p>\n

Gateway<\/em><\/strong>\u00a0is the schematic entry for the Analog\/Mixed Signal\/RF Design design environment. The\u00a0Gateway<\/em><\/strong>\u00a0schematic is netlisted for\u00a0SmartSpice-RF<\/strong><\/em>\u00a0and tightly integrated for running simulations concurrent with the schematic.<\/p>\n

This article shows the basic steps needed to take a design from schematic entry to simulation using the TSMC 018 MM\/RF process and a set of Silvaco tools. These steps can be broken down into the following tasks.<\/p>\n