{"id":29167,"date":"2006-05-01T00:04:43","date_gmt":"2006-05-01T00:04:43","guid":{"rendered":"https:\/\/silvaco.com\/uncategorized\/interconnect-parasitic-extraction-of-bicmos-cell-using-silvaco-clever\/"},"modified":"2021-07-08T18:25:54","modified_gmt":"2021-07-09T01:25:54","slug":"interconnect-parasitic-extraction-of-bicmos-cell-using-silvaco-clever","status":"publish","type":"post","link":"https:\/\/silvaco.com\/ja\/simulation-standard\/interconnect-parasitic-extraction-of-bicmos-cell-using-silvaco-clever\/","title":{"rendered":"Interconnect Parasitic Extraction of BiCMOS Cell Using Silvaco Clever"},"content":{"rendered":"
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Interconnect Parasitic Extraction of BiCMOS Cell Using Silvaco\u00a0CLEVER<\/em><\/h1>\n

1. Introduction<\/h3>\n

Interconnect parasitic effects play a very important role in modern integrated circuit design, especially for digital circuit. This article presents how a cell level BiCMOS nand gate is extracted with R (resistances) and C (capacitances). The extracted RC result is then back-annotated into SPICE netlist for POST verification purpose. We used the Silvaco product,\u00a0CLEVER<\/em><\/strong>\u00a0which is a highly accurate 3D process interconnect RC extractor.<\/p>\n

2. Description of BiCMOS Cell Extractor and Simulation Results<\/p>\n

2.1 Overview<\/p>\n

In order to perform parasitic extraction, we need a layout file and a command file. Command file defines the physical processes and starts the interconnect simulation. It also generate the 3D structure files and SPICE netlist. The layout file can be in the form of a GDS format. Besides, we may also need a layer mapping file which provides a name for each layer and a rule file which is similar to the technology file to define active device and connectivity. Figure 1 shows the data flow inside\u00a0CLEVER<\/strong><\/em>. Figure 3 is the saved layout after loading the layer mapping file. The new layer names are showed in this layout.<\/p>\n<\/div><\/section><\/div>

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