{"id":28963,"date":"2014-07-01T20:14:59","date_gmt":"2014-07-01T20:14:59","guid":{"rendered":"https:\/\/silvaco.com\/uncategorized\/multiple-seu-strike-simulations-on-a-six-transistor-20nm-sram-cell\/"},"modified":"2026-10-16T08:50:22","modified_gmt":"2026-10-16T15:50:22","slug":"multiple-seu-strike-simulations-on-a-six-transistor-20nm-sram-cell","status":"publish","type":"post","link":"https:\/\/silvaco.com\/ja\/simulation-standard\/multiple-seu-strike-simulations-on-a-six-transistor-20nm-sram-cell\/","title":{"rendered":"Multiple SEU Strike Simulations on a Six Transistor 20nm SRAM Cell"},"content":{"rendered":"

Multiple SEU Strike Simulations on a Six Transistor 20nm SRAM Cell<\/h1>\n

Introduction<\/h3>\n

It is often not realized that more than one Single Event Upset (SEU) statement can be used in a simulation. Each SEU statement can locate a strike anywhere in the semiconductor and at any time during the transient, offering a range of simulation possibilities. One possible use for simulating multiple SEU strikes is for simulating spallation events, where a high energy particle, such as a cosmic ray, suffers a nuclear interaction, producing one or more different sources of ionizing particle at the nuclear reaction site. In this article, we will, demonstrate two SEU strikes in different locations at two different times on a full six transistor 22nm SRAM cell, including four layers of metal interconnect.<\/p>\n

\"\"<\/p>\n

Download Simulation Standard<\/a><\/p>\n","protected":false},"excerpt":{"rendered":"

It is often not realized that more than one Single Event Upset (SEU) statement can be used in a simulation. Each SEU statement can locate a strike anywhere in the semiconductor and at any time during the transient, offering a range of simulation possibilities. One possible use for simulating multiple SEU strikes is for simulating spallation events, where a high energy particle, such as a cosmic ray, suffers a nuclear interaction, producing one or more different sources of ionizing particle at the nuclear reaction site. In this article, we will, demonstrate two SEU strikes in different locations at two different times on a full six transistor 22nm SRAM cell, including four layers of metal interconnect.<\/p>\n","protected":false},"author":12,"featured_media":19661,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"inline_featured_image":false,"footnotes":""},"categories":[7570],"tags":[],"class_list":["post-28963","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-simulation-standard","entry","has-media"],"yoast_head":"\nMultiple SEU Strike Simulations on a Six Transistor 20nm SRAM Cell - Silvaco<\/title>\n<meta name=\"description\" content=\"It is often not realized that more than one Single Event Upset (SEU) statement can be used in a simulation.\" \/>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link rel=\"canonical\" href=\"https:\/\/silvaco.com\/ja\/simulation-standard\/multiple-seu-strike-simulations-on-a-six-transistor-20nm-sram-cell\/\" \/>\n<meta property=\"og:locale\" content=\"ja_JP\" \/>\n<meta property=\"og:type\" content=\"article\" \/>\n<meta property=\"og:title\" content=\"Multiple SEU Strike Simulations on a Six Transistor 20nm SRAM Cell\" \/>\n<meta property=\"og:description\" content=\"It is often not realized that more than one Single Event Upset (SEU) statement can be used in a simulation.\" \/>\n<meta property=\"og:url\" content=\"https:\/\/silvaco.com\/ja\/simulation-standard\/multiple-seu-strike-simulations-on-a-six-transistor-20nm-sram-cell\/\" \/>\n<meta property=\"og:site_name\" content=\"Silvaco\" \/>\n<meta property=\"article:publisher\" content=\"https:\/\/www.facebook.com\/SilvacoSoftware\/\" \/>\n<meta property=\"article:published_time\" content=\"2014-07-01T20:14:59+00:00\" \/>\n<meta property=\"article:modified_time\" content=\"2026-10-16T15:50:22+00:00\" \/>\n<meta property=\"og:image\" content=\"https:\/\/silvaco.com\/wp-content\/uploads\/2020\/03\/simstd_Q3_2014_a2.jpg\" \/>\n\t<meta property=\"og:image:width\" content=\"782\" \/>\n\t<meta property=\"og:image:height\" content=\"1012\" \/>\n\t<meta property=\"og:image:type\" content=\"image\/jpeg\" \/>\n<meta name=\"author\" content=\"Casey Molver\" \/>\n<meta name=\"twitter:card\" content=\"summary_large_image\" \/>\n<meta name=\"twitter:creator\" content=\"@SilvacoSoftware\" \/>\n<meta name=\"twitter:site\" content=\"@SilvacoSoftware\" \/>\n<meta name=\"twitter:label1\" content=\"\u57f7\u7b46\u8005\" \/>\n\t<meta name=\"twitter:data1\" content=\"Casey Molver\" \/>\n\t<meta name=\"twitter:label2\" content=\"\u63a8\u5b9a\u8aad\u307f\u53d6\u308a\u6642\u9593\" \/>\n\t<meta name=\"twitter:data2\" content=\"1 minute\" \/>\n<script type=\"application\/ld+json\" class=\"yoast-schema-graph\">{\"@context\":\"https:\\\/\\\/schema.org\",\"@graph\":[{\"@type\":\"Article\",\"@id\":\"https:\\\/\\\/silvaco.com\\\/ja\\\/simulation-standard\\\/multiple-seu-strike-simulations-on-a-six-transistor-20nm-sram-cell\\\/#article\",\"isPartOf\":{\"@id\":\"https:\\\/\\\/silvaco.com\\\/ja\\\/simulation-standard\\\/multiple-seu-strike-simulations-on-a-six-transistor-20nm-sram-cell\\\/\"},\"author\":{\"name\":\"Casey Molver\",\"@id\":\"https:\\\/\\\/silvaco.com\\\/ja\\\/#\\\/schema\\\/person\\\/2763eb741ca5ac04477fdff50ed84c80\"},\"headline\":\"Multiple SEU Strike Simulations on a Six Transistor 20nm SRAM Cell\",\"datePublished\":\"2014-07-01T20:14:59+00:00\",\"dateModified\":\"2026-10-16T15:50:22+00:00\",\"mainEntityOfPage\":{\"@id\":\"https:\\\/\\\/silvaco.com\\\/ja\\\/simulation-standard\\\/multiple-seu-strike-simulations-on-a-six-transistor-20nm-sram-cell\\\/\"},\"wordCount\":141,\"image\":{\"@id\":\"https:\\\/\\\/silvaco.com\\\/ja\\\/simulation-standard\\\/multiple-seu-strike-simulations-on-a-six-transistor-20nm-sram-cell\\\/#primaryimage\"},\"thumbnailUrl\":\"https:\\\/\\\/silvaco.com\\\/wp-content\\\/uploads\\\/2020\\\/03\\\/simstd_Q3_2014_a2.jpg\",\"articleSection\":[\"Simulation Standard\"],\"inLanguage\":\"ja\"},{\"@type\":\"WebPage\",\"@id\":\"https:\\\/\\\/silvaco.com\\\/ja\\\/simulation-standard\\\/multiple-seu-strike-simulations-on-a-six-transistor-20nm-sram-cell\\\/\",\"url\":\"https:\\\/\\\/silvaco.com\\\/ja\\\/simulation-standard\\\/multiple-seu-strike-simulations-on-a-six-transistor-20nm-sram-cell\\\/\",\"name\":\"Multiple SEU Strike Simulations on a Six Transistor 20nm SRAM Cell - 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