{"id":28963,"date":"2014-07-01T20:14:59","date_gmt":"2014-07-01T20:14:59","guid":{"rendered":"https:\/\/silvaco.com\/uncategorized\/multiple-seu-strike-simulations-on-a-six-transistor-20nm-sram-cell\/"},"modified":"2021-07-08T18:19:01","modified_gmt":"2021-07-09T01:19:01","slug":"multiple-seu-strike-simulations-on-a-six-transistor-20nm-sram-cell","status":"publish","type":"post","link":"https:\/\/silvaco.com\/ja\/simulation-standard\/multiple-seu-strike-simulations-on-a-six-transistor-20nm-sram-cell\/","title":{"rendered":"Multiple SEU Strike Simulations on a Six Transistor 20nm SRAM Cell"},"content":{"rendered":"
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Multiple SEU Strike Simulations on a Six Transistor 20nm SRAM Cell<\/h1>\n

Introduction<\/h3>\n

It is often not realized that more than one Single Event Upset (SEU) statement can be used in a simulation. Each SEU statement can locate a strike anywhere in the semiconductor and at any time during the transient, offering a range of simulation possibilities. One possible use for simulating multiple SEU strikes is for simulating spallation events, where a high energy particle, such as a cosmic ray, suffers a nuclear interaction, producing one or more different sources of ionizing particle at the nuclear reaction site. In this article, we will, demonstrate two SEU strikes in different locations at two different times on a full six transistor 22nm SRAM cell, including four layers of metal interconnect.<\/p>\n<\/div><\/section><\/div>

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