Cryogenic electronics plays a fundamental role in several applications, such as spacecraft, high-energy physics experiments, metrology, superconductive astronomical detectors and, with the increased interest in quantum computing, the manipulation of quantum bits (qubits) [1]. Outstanding characteristics have been reported for advanced CMOS technologies operating at cryogenic temperature in terms of on-state current, leakage current, subthreshold swing, and transconductance [2]. This represents an excellent opportunity to use such advanced technologies to design and implement a quantum computing control system (including multiplexers, LNAs, and RF oscillators) and introduce it inside the refrigerator together with the qubits [3]. Another recently growing field of application is the cryogenic silicon photonics [4].<\/p>\n
However, finding the optimal trade-off in the design of semiconductor devices, including p-n and p-i-n junction based devices, MOSFETs, and CMOS circuits is challenging due to the lack of efficient physics-based models valid down to cryogenic and deep-cryogenic temperatures – typically 4.2 K (liquid helium) or even below for quantum computing applications. Physics-based analysis and design of devices operating below 77 K have been held up by the numerical difficulties of modeling and simulation in this temperature range [5, 6]. The intrinsic carrier concentration becomes extremely small at cryogenic temperatures, which has its inevitable root in the exponential temperature scaling of the Fermi-Dirac and Boltzmann statistics.<\/p>\n
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