{"id":58609,"date":"2024-11-26T16:20:29","date_gmt":"2024-11-27T00:20:29","guid":{"rendered":"https:\/\/silvaco.com\/?page_id=58609"},"modified":"2026-01-08T14:33:44","modified_gmt":"2026-01-08T22:33:44","slug":"surge-virtual-event-japan-2025","status":"publish","type":"page","link":"https:\/\/silvaco.com\/ja\/corporate\/surge\/surge-virtual-event-japan-2025\/","title":{"rendered":"SURGE Virtual Event Japan 2025"},"content":{"rendered":"<div id='full_slider_1'  class='avia-fullwidth-slider main_color avia-shadow   avia-builder-el-0  el_before_av_section  avia-builder-el-first   container_wrap fullsize' style=' '  ><div   data-size='featured'  data-lightbox_size='large'  data-animation='slide'  data-conditional_play=''  data-ids='63862'  data-video_counter='0'  data-autoplay='false'  data-bg_slider='false'  data-slide_height=''  data-handle='av_slideshow_full'  data-interval='5'  data-class=' '  data-el_id=''  data-css_id=''  data-scroll_down=''  data-control_layout='av-control-default'  data-custom_markup=''  data-perma_caption=''  data-autoplay_stopper=''  data-image_attachment=''  data-min_height='0px'  data-lazy_loading='disabled'  data-src=''  data-position='top left'  data-repeat='no-repeat'  data-attach='scroll'  data-stretch=''  data-default-height='28.666666666667'  class='avia-slideshow avia-slideshow-1  av-control-default av-default-height-applied avia-slideshow-featured av_slideshow_full   avia-slide-slider '  itemprop=\"image\" itemscope=\"itemscope\" itemtype=\"https:\/\/schema.org\/ImageObject\" ><ul class='avia-slideshow-inner ' style='padding-bottom: 15.933333333333%;' ><li  class=' av-single-slide slide-1 ' ><div data-rel='slideshow-1' class='avia-slide-wrap '   ><img decoding=\"async\" class=\"wp-image-63862 avia-img-lazy-loading-not-63862\"  src=\"https:\/\/silvaco.com\/wp-content\/uploads\/2026\/01\/SURGE_LandingPage_Banner3-1500x239.jpg\" width=\"1500\" height=\"239\" title='SURGE_LandingPage_Banner3' alt=''  itemprop=\"thumbnailUrl\"   \/><\/div><\/li><\/ul><\/div><\/div>\n<div id='av_section_1'  class='avia-section main_color avia-section-default avia-no-border-styling  avia-bg-style-scroll  avia-builder-el-1  el_after_av_slideshow_full  el_before_av_section   container_wrap fullsize' style=' '  ><div class='container' ><div class='template-page content  av-content-full alpha units'><div class='post-entry post-entry-type-page post-entry-58609'><div class='entry-content-wrapper clearfix'>\n<div class=\"flex_column av_one_full  flex_column_div av-zero-column-padding first  avia-builder-el-2  avia-builder-el-no-sibling  \" style='border-radius:0px; '><section class=\"av_textblock_section \"  itemscope=\"itemscope\" itemtype=\"https:\/\/schema.org\/CreativeWork\" ><div class='avia_textblock  '   itemprop=\"text\" ><h1 class=\"p1\"><span class=\"s1\">SURGE Virtual Event Japan 2025<\/span><\/h1>\n<p><strong>\u958b\u50ac\u65e5\u6642\uff1a2025\/1\/23 10:00 (JST)<\/strong><\/p>\n<div class=\"ewa-rteLine\">\n<p>SURGE (Silvaco UserRs Global Event) \u306f\u3001Silvaco \u304c\u958b\u50ac\u3059\u308b\u4e16\u754c\u898f\u6a21\u306e\u30a4\u30d9\u30f3\u30c8\u3067\u3059\u3002<\/p>\n<p>SURGE \u306f\u3001TCAD\u3001EDA\u3001IP \u306e\u5206\u91ce\u306b\u304a\u3051\u308b\u9ad8\u5ea6\u306a\u534a\u5c0e\u4f53\u8a2d\u8a08\u306e\u305f\u3081\u306e\u65b0\u3057\u3044\u6280\u8853\u306b\u3064\u3044\u3066\u8b70\u8ad6\u3057\u3001\u30e6\u30fc\u30b6\u30fc \u30a8\u30af\u30b9\u30da\u30ea\u30a8\u30f3\u30b9\u3092\u5171\u6709\u3057\u3001\u9769\u65b0\u7684\u306a\u6280\u8853\u3092\u767a\u898b\u3059\u308b\u305f\u3081\u306e\u30a4\u30d9\u30f3\u30c8\u3067\u3059\u3002\u30aa\u30f3\u30e9\u30a4\u30f3\u3067\u958b\u50ac\u3055\u308c\u307e\u3059\u3002<\/p>\n<div class=\"ewa-rteLine\">\u5f53\u65e5\u306e\u8b1b\u6f14\u30d3\u30c7\u30aa\u3092\u30aa\u30f3\u30c7\u30de\u30f3\u30c9\u306b\u3066\u8996\u8074\u3044\u305f\u3060\u3051\u307e\u3059\u3002<\/div>\n<div class=\"ewa-rteLine\">\u8996\u8074\u306b\u306f\u30b7\u30eb\u30d0\u30b3\u30fb\u30a2\u30ab\u30a6\u30f3\u30c8\u304c\u5fc5\u8981\u3067\u3059\u3002\uff08\u304a\u6301\u3061\u3067\u306a\u3044\u65b9\u306f\u3053\u306e\u6a5f\u4f1a\u306b\u767b\u9332\u3092\u304a\u9858\u3044\u3044\u305f\u3057\u307e\u3059\uff09<\/div>\n<\/div>\n<div><\/div>\n<\/div><\/section><\/div>\n\n<\/div><\/div><\/div><!-- close content main div --><\/div><\/div><div id='av_section_2'  class='avia-section main_color avia-section-no-padding avia-no-border-styling  avia-bg-style-scroll  avia-builder-el-4  el_after_av_section  el_before_av_section   container_wrap fullsize' style=' '  ><div class='container' ><div class='template-page content  av-content-full alpha units'><div class='post-entry post-entry-type-page post-entry-58609'><div class='entry-content-wrapper clearfix'>\n<div class=\"flex_column av_one_full  flex_column_div av-zero-column-padding first  avia-builder-el-5  avia-builder-el-no-sibling  \" style='border-radius:0px; '><section class=\"av_textblock_section \"  itemscope=\"itemscope\" itemtype=\"https:\/\/schema.org\/CreativeWork\" ><div class='avia_textblock  '   itemprop=\"text\" ><h1 style=\"text-align: center;\"><strong>AGENDA<\/strong><\/h1>\n<\/div><\/section><br \/>\n<\/p><\/div>\n\n<\/div><\/div><\/div><!-- close content main div --><\/div><\/div><div id='babak_t'  class='avia-section main_color avia-section-default avia-no-border-styling  avia-bg-style-scroll  mfp-hide  container_wrap fullsize' style=' '  ><div class='container' ><div class='template-page content  av-content-full alpha units'><div class='post-entry post-entry-type-page post-entry-58609'><div class='entry-content-wrapper clearfix'>\n<div class=\"flex_column av_one_fourth  flex_column_div av-zero-column-padding first  \" style='border-radius:0px; '><div  class='avia-image-container  av-styling-    avia-align-center '  itemprop=\"image\" itemscope=\"itemscope\" itemtype=\"https:\/\/schema.org\/ImageObject\"  ><div class='avia-image-container-inner'><div class='avia-image-overlay-wrap'><img decoding=\"async\" class='wp-image-19988 avia-img-lazy-loading-not-19988 avia_image' src=\"https:\/\/silvaco.com\/wp-content\/uploads\/2020\/03\/babak-210x300.jpg\" alt='' title='babak' height=\"300\" width=\"210\"  itemprop=\"thumbnailUrl\" srcset=\"https:\/\/silvaco.com\/wp-content\/uploads\/2020\/03\/babak-210x300.jpg 210w, https:\/\/silvaco.com\/wp-content\/uploads\/2020\/03\/babak-26x37.jpg 26w, https:\/\/silvaco.com\/wp-content\/uploads\/2020\/03\/babak-39x55.jpg 39w, https:\/\/silvaco.com\/wp-content\/uploads\/2020\/03\/babak-34x48.jpg 34w, https:\/\/silvaco.com\/wp-content\/uploads\/2020\/03\/babak.jpg 400w\" sizes=\"(max-width: 210px) 100vw, 210px\" \/><\/div><\/div><\/div><\/div><div class=\"flex_column av_three_fourth  flex_column_div av-zero-column-padding   \" style='border-radius:0px; '><section class=\"av_textblock_section \"  itemscope=\"itemscope\" itemtype=\"https:\/\/schema.org\/CreativeWork\" ><div class='avia_textblock  '   itemprop=\"text\" ><h3 class=\"p1\"><span class=\"s1\">Speaker:<\/span><\/h3>\n<p class=\"p1\"><strong><span class=\"s1\">Dr. Babak Taheri<br \/>\n<\/span><\/strong><strong>Chief Executive Officer and Director<span class=\"s1\">, Silvaco<\/span><\/strong><\/p>\n<p class=\"p3\"><span class=\"s1\">Babak A. Taheri, Ph.D. has served as Chief Executive Officer and a board member of Silvaco since August 2019, with a brief pause between September and November 2021. Prior to becoming CEO, he served as Chief Technology Officer and Executive Vice President of Products from October 2018 to August 2019.<\/span><\/p>\n<p class=\"p3\"><span class=\"s1\">Before joining Silvaco, Dr. Taheri was the CEO and President of Integrated Biosensing Technologies (IBT), an advisory and consulting firm, from May 2015 to October 2018. Dr. Taheri serves on the board of directors of Sunright Limited (Singapore: SGX), a provider of advanced semiconductor test and burn-in services. He has also served on advisory boards, including MEMS World Summit, Novasentis, AGCM, ALEA Labs, Silverlake Sumeru, Lion Point Capital, and was a member of the governing council of ESDA Alliance (2019-2021). He currently chairs the advisory board for the Electrical Engineering Department at the University of California, Davis.<\/span><\/p>\n<p class=\"p3\"><span class=\"s1\">Dr. Taheri has held leadership roles at several companies, including VP &amp; GM at Freescale Semiconductor (now NXP), where he received the \u201cDiamond Chip Award\u201d (2013, 2014) and was named MEMS &amp; Sensors Executive of the Year (2014). He has also served as VP\/GM at Cypress Semiconductors, earning \u201cThe Perfect Project Award\u201d in 2003, and was instrumental in acquiring Ramtron for the business he was managing. His experience includes roles at Invensense (now TDK), SRI International, and Apple.<\/span><\/p>\n<p class=\"p3\"><span class=\"s1\">Dr. Taheri holds a B.S. in Engineering from San Francisco State University, an M.S. in Electrical Engineering from San Jose State University, and a Ph.D. in Biomedical Engineering (with concentrations in Electrical Engineering and Neuroscience) from the University of California, Davis. In 2015, he received the Distinguished Engineering Alumni Medal (DEAM) from UC Davis. His most recent book, \u201cArtificial Sensors Shape the Six Pillars of Our Lives,\u201d was published in 2021.<\/span><\/p>\n<\/div><\/section><\/div>\n\n<\/div><\/div><\/div><!-- close content main div --><\/div><\/div><div id='wally_w'  class='avia-section main_color avia-section-default avia-no-border-styling  avia-bg-style-scroll  mfp-hide  container_wrap fullsize' style=' '  ><div class='container' ><div class='template-page content  av-content-full alpha units'><div class='post-entry post-entry-type-page post-entry-58609'><div class='entry-content-wrapper clearfix'>\n<div class=\"flex_column av_one_fourth  flex_column_div av-zero-column-padding first  \" style='border-radius:0px; '><div  class='avia-image-container  av-styling-    avia-align-center '  itemprop=\"image\" itemscope=\"itemscope\" itemtype=\"https:\/\/schema.org\/ImageObject\"  ><div class='avia-image-container-inner'><div class='avia-image-overlay-wrap'><img decoding=\"async\" class='wp-image-44033 avia-img-lazy-loading-not-44033 avia_image' src=\"https:\/\/silvaco.com\/wp-content\/uploads\/2022\/11\/wally_r_headshot.jpg\" alt='' title='wally_r_headshot' height=\"300\" width=\"210\"  itemprop=\"thumbnailUrl\" srcset=\"https:\/\/silvaco.com\/wp-content\/uploads\/2022\/11\/wally_r_headshot.jpg 210w, https:\/\/silvaco.com\/wp-content\/uploads\/2022\/11\/wally_r_headshot-26x37.jpg 26w, https:\/\/silvaco.com\/wp-content\/uploads\/2022\/11\/wally_r_headshot-39x55.jpg 39w, https:\/\/silvaco.com\/wp-content\/uploads\/2022\/11\/wally_r_headshot-34x48.jpg 34w\" sizes=\"(max-width: 210px) 100vw, 210px\" \/><\/div><\/div><\/div><\/div><div class=\"flex_column av_three_fourth  flex_column_div av-zero-column-padding   \" style='border-radius:0px; '><section class=\"av_textblock_section \"  itemscope=\"itemscope\" itemtype=\"https:\/\/schema.org\/CreativeWork\" ><div class='avia_textblock  '   itemprop=\"text\" ><h1>AI Takes EDA to the Next Level<\/h1>\n<h3>Speaker:<\/h3>\n<p><strong>Wally Rhines<br \/>\n<\/strong><strong>President and CEO of Cornami and Silvaco Board Member\u200b<\/strong><\/p>\n<p>Walden C. Rhines, Ph.D., has served as a member of our board of directors and as a member of our audit committee since September 2022. Since March 2020, Dr. Rhines has served as President and Chief Executive Officer of Cornami, Inc., a fabless semiconductor company. Since 2015, Dr. Rhines has also served as a member of the board of directors and as chair of the compensation committee of Qorvo, Inc. (Nasdaq: QRVO), a semiconductor company, since January 2015 and its chairman since November 2023. He served as a member of the board of directors of PTK Acquisition Corp. (NYSE: PTK), a special purpose acquisition company from July 2020 until September 2021 and served on its audit, nominating and compensation committees. From October 1993 to March 2017, Dr. Rhines served as President and Chief Executive Officer of Mentor Graphics Corporation, an EDA company, and chairman of its board of directors from 2000 until its acquisition by Siemens in March 2017, pursuant to which the company was renamed Mentor Graphics, a Siemens Business. Following the acquisition, Dr. Rhines served as President and Chief Executive Officer of Siemens EDA (formerly Mentor Graphics, a Siemens Business), from March 2017 to October 2018, after which he served as its Chief Executive Officer Emeritus until September 2020. Dr. Rhines received a B.S.E. in metallurgical engineering from the University of Michigan, an M.S. and Ph.D. in materials science and engineering from Stanford University, and a M.B.A. from the Southern Methodist University, Cox School of Business.<\/p>\n<\/div><\/section><\/div>\n\n<\/div><\/div><\/div><!-- close content main div --><\/div><\/div><div id='peter_g'  class='avia-section main_color avia-section-default avia-no-border-styling  avia-bg-style-scroll  mfp-hide  container_wrap fullsize' style=' '  ><div class='container' ><div class='template-page content  av-content-full alpha units'><div class='post-entry post-entry-type-page post-entry-58609'><div class='entry-content-wrapper clearfix'>\n<div class=\"flex_column av_one_fourth  flex_column_div av-zero-column-padding first  \" style='border-radius:0px; '><div  class='avia-image-container  av-styling-    avia-align-center '  itemprop=\"image\" itemscope=\"itemscope\" itemtype=\"https:\/\/schema.org\/ImageObject\"  ><div class='avia-image-container-inner'><div class='avia-image-overlay-wrap'><img decoding=\"async\" class='wp-image-58295 avia-img-lazy-loading-not-58295 avia_image' src=\"https:\/\/silvaco.com\/wp-content\/uploads\/2024\/11\/Peter_Griffin.png\" alt='' title='Peter_Griffin' height=\"209\" width=\"211\"  itemprop=\"thumbnailUrl\" srcset=\"https:\/\/silvaco.com\/wp-content\/uploads\/2024\/11\/Peter_Griffin.png 211w, https:\/\/silvaco.com\/wp-content\/uploads\/2024\/11\/Peter_Griffin-80x80.png 80w, https:\/\/silvaco.com\/wp-content\/uploads\/2024\/11\/Peter_Griffin-36x36.png 36w, https:\/\/silvaco.com\/wp-content\/uploads\/2024\/11\/Peter_Griffin-37x37.png 37w, https:\/\/silvaco.com\/wp-content\/uploads\/2024\/11\/Peter_Griffin-56x55.png 56w, https:\/\/silvaco.com\/wp-content\/uploads\/2024\/11\/Peter_Griffin-48x48.png 48w\" sizes=\"(max-width: 211px) 100vw, 211px\" \/><\/div><\/div><\/div><\/div><div class=\"flex_column av_three_fourth  flex_column_div av-zero-column-padding   \" style='border-radius:0px; '><section class=\"av_textblock_section \"  itemscope=\"itemscope\" itemtype=\"https:\/\/schema.org\/CreativeWork\" ><div class='avia_textblock  '   itemprop=\"text\" ><h1>NanoHub Workforce Development<\/h1>\n<h3>Speaker:<\/h3>\n<p><strong>Dr. Peter\u00a0Griffin<\/strong><\/p>\n<p>Dr. Peter\u00a0Griffin is an expert in microfabrication, having co-authored one of the most widely used textbooks in the area with Prof. Jim Plummer titled \u201cIntegrated Circuit Fabrication \u2013 Science and Technology\u201d published by Cambridge University Press in 2024. He has significant hands-on experience in simulating and building semiconductor structures and teaching semiconductor technology courses at Stanford.<\/p>\n<p>For\u00a0the past two decades, he has performed interdisciplinary work at the Stanford Genome Technology Center (SGTC) with a particular emphasis on digital microfluidics. He is particularly interested in how semiconductor technology can contribute to bioengineering and was the lead author on major DARPA, NIH and SRC grants in various application areas. Griffin has enjoyed long term collaborations with leading researchers on those interdisciplinary grants which has made his time at Stanford very productive. Griffin\u2019s current interest is on impedance measurements for diagnostics in the laboratory of Prof. Lars Steinmetz at SGTC.<\/p>\n<\/div><\/section><\/div>\n\n<\/div><\/div><\/div><!-- close content main div --><\/div><\/div><div id='eric_g'  class='avia-section main_color avia-section-default avia-no-border-styling  avia-bg-style-scroll  mfp-hide  container_wrap fullsize' style=' '  ><div class='container' ><div class='template-page content  av-content-full alpha units'><div class='post-entry post-entry-type-page post-entry-58609'><div class='entry-content-wrapper clearfix'>\n<div class=\"flex_column av_one_fourth  flex_column_div av-zero-column-padding first  \" style='border-radius:0px; '><div  class='avia-image-container  av-styling-    avia-align-center '  itemprop=\"image\" itemscope=\"itemscope\" itemtype=\"https:\/\/schema.org\/ImageObject\"  ><div class='avia-image-container-inner'><div class='avia-image-overlay-wrap'><img decoding=\"async\" class='wp-image-20018 avia-img-lazy-loading-not-20018 avia_image' src=\"https:\/\/silvaco.com\/wp-content\/uploads\/2020\/03\/eric_g_lg-210x300.jpg\" alt='Eric Guichard' title='Eric Guichard' height=\"300\" width=\"210\"  itemprop=\"thumbnailUrl\" srcset=\"https:\/\/silvaco.com\/wp-content\/uploads\/2020\/03\/eric_g_lg-210x300.jpg 210w, https:\/\/silvaco.com\/wp-content\/uploads\/2020\/03\/eric_g_lg-26x37.jpg 26w, https:\/\/silvaco.com\/wp-content\/uploads\/2020\/03\/eric_g_lg-39x55.jpg 39w, https:\/\/silvaco.com\/wp-content\/uploads\/2020\/03\/eric_g_lg-34x48.jpg 34w, https:\/\/silvaco.com\/wp-content\/uploads\/2020\/03\/eric_g_lg.jpg 400w\" sizes=\"(max-width: 210px) 100vw, 210px\" \/><\/div><\/div><\/div><\/div><div class=\"flex_column av_three_fourth  flex_column_div av-zero-column-padding   \" style='border-radius:0px; '><section class=\"av_textblock_section \"  itemscope=\"itemscope\" itemtype=\"https:\/\/schema.org\/CreativeWork\" ><div class='avia_textblock  '   itemprop=\"text\" ><h1 class=\"p1\"><span class=\"s1\">TCAD Update <\/span><\/h1>\n<h3 class=\"p1\"><span class=\"s1\">Abstract:<\/span><\/h3>\n<p class=\"p1\"><span class=\"s1\">Dr. Guichard will provide an update on Silvaco TCAD Victory simulation products, the importance of TCAD in the development of next-generation devices, and the future of TCAD development.<\/span><\/p>\n<h3 class=\"p1\"><span class=\"s1\">Speaker:<\/span><\/h3>\n<p class=\"p3\"><strong><span class=\"s1\">Dr. Eric Guichard<br \/>\n<\/span><span class=\"s1\">SVP and GM of TCAD Business Unit &#8211; Silvaco<\/span><\/strong><\/p>\n<p class=\"p1\"><span class=\"s1\">Eric Guichard, Ph.D., has served as our Senior Vice President and General Manager of our TCAD division since November 2012, and served as our Vice President of Applications from July 2008 to November 2012. From September 1995 to July 2008, Dr. Guichard served in various roles with Silvaco SA, formerly known as Silvaco Data Systems, one of our wholly-owned subsidiaries, including as an applications engineer. Dr. Guichard received a M.S. in material science and a Ph.D. in semiconductor physics from Instituto Polit\u00e9cnico Nacional de Grenoble, France.<\/span><\/p>\n<\/div><\/section><\/div>\n\n<\/div><\/div><\/div><!-- close content main div --><\/div><\/div><div id='sanam_mt'  class='avia-section main_color avia-section-default avia-no-border-styling  avia-bg-style-scroll  mfp-hide  container_wrap fullsize' style=' '  ><div class='container' ><div class='template-page content  av-content-full alpha units'><div class='post-entry post-entry-type-page post-entry-58609'><div class='entry-content-wrapper clearfix'>\n<div class=\"flex_column av_one_fourth  flex_column_div av-zero-column-padding first  \" style='border-radius:0px; '><div  class='avia-image-container  av-styling-    avia-align-center '  itemprop=\"image\" itemscope=\"itemscope\" itemtype=\"https:\/\/schema.org\/ImageObject\"  ><div class='avia-image-container-inner'><div class='avia-image-overlay-wrap'><img decoding=\"async\" class='wp-image-58333 avia-img-lazy-loading-not-58333 avia_image' src=\"https:\/\/silvaco.com\/wp-content\/uploads\/2024\/11\/Sanam-Moslemi-Tabrizi.jpg\" alt='' title='Sanam Moslemi-Tabrizi' height=\"169\" width=\"131\"  itemprop=\"thumbnailUrl\" srcset=\"https:\/\/silvaco.com\/wp-content\/uploads\/2024\/11\/Sanam-Moslemi-Tabrizi.jpg 131w, https:\/\/silvaco.com\/wp-content\/uploads\/2024\/11\/Sanam-Moslemi-Tabrizi-29x37.jpg 29w, https:\/\/silvaco.com\/wp-content\/uploads\/2024\/11\/Sanam-Moslemi-Tabrizi-43x55.jpg 43w, https:\/\/silvaco.com\/wp-content\/uploads\/2024\/11\/Sanam-Moslemi-Tabrizi-37x48.jpg 37w\" sizes=\"(max-width: 131px) 100vw, 131px\" \/><\/div><\/div><\/div><\/div><div class=\"flex_column av_three_fourth  flex_column_div av-zero-column-padding   \" style='border-radius:0px; '><section class=\"av_textblock_section \"  itemscope=\"itemscope\" itemtype=\"https:\/\/schema.org\/CreativeWork\" ><div class='avia_textblock  '   itemprop=\"text\" ><h1>Low-temperature Behavior in Nanowire Transistors by Quantum Transport Simulation<\/h1>\n<h3>Abstract:<\/h3>\n<p>Quantum effects dominate at the nanoscale, where classical simulation tools lack the capability to accurately capture or observe these phenomena. Ciena\u2019s analog design process relies significantly on provided models; however, as we scale, these models become increasingly less accurate. Consequently, we have initiated analysis and verification efforts to develop our own models to account for quantum effects. Additionally, we are required to analyze device behavior at cryogenic temperatures used in qubit technology.<\/p>\n<p>Quantum device modeling requires specialized tools that can solve the Poisson-Schr\u00f6dinger equations self-consistently. Silvaco\u2019s Victory Atomistic tool easily met our initial requirements, but we quickly identified additional complexities, which prompted a close collaboration between Silvaco and Ciena teams to refine and enhance the tool.<\/p>\n<p>Through this collaboration, we have developed an engine that closely simulates our in-house devices. Despite limited information about the fabrication process, we worked diligently to design a device model that approximates Ciena\u2019s actual devices. While the model does not replicate measurements exactly, the trend of Victory Atomistic\u2019s simulation graphs aligns well with the lab data for our 5nm devices at room temperature.<\/p>\n<p>In advancing our qubit technology research, we successfully measured and observed device behavior at extremely low temperatures; however, the process was both costly and complex. To streamline our approach, we are working to replace physical measurements with device simulations, and Silvaco\u2019s ViA shows promising potential in this area. At these extreme low temperatures, the tool initially faced numerical convergence issues, but with iterative improvements, these challenges are gradually being resolved. Future work will focus on further enhancing ViA, particularly to achieve stable convergence at lower cryogenic temperatures and lower bias conditions.<\/p>\n<h3>Speaker:<\/h3>\n<p><strong>Sanam Moslemi-Tabrizi<\/strong><br \/>\n<strong>Analog Engineer, Ciena<\/strong><\/p>\n<p>Bio Sanam Moslemi-Tabrizi received her B.Eng. in Electrical Engineering from Tabriz University in 1996, specializing in Analog Circuits. She completed her M.Sc. in Electrical Engineering at Concordia University in 2007, focusing on Solid State Devices. Her master\u2019s thesis in Computational Quantum Mechanics involved computing eigenstates for multidimensional nanostructures.<\/p>\n<p>As a Research Associate in the Department of Electronics at Carleton University, Sanam conducted significant research in electromagnetics, where she developed a Full Vectorial Mode Solver and Waveguide Simulator based on Yee cell Finite-Difference Frequency-Domain (FDFD) methods. This tool supported her work in designing a 2D beam-scanning system based on Optical Phased Array (OPA) technology for LiDAR applications.<\/p>\n<p>Currently, Sanam is an Analog Engineer at Ciena, responsible for the verification of analog circuits and for development of advanced quantum device models for Ciena\u2019s next-generation products.<\/p>\n<\/div><\/section><\/div>\n\n<\/div><\/div><\/div><!-- close content main div --><\/div><\/div><div id='lado_f'  class='avia-section main_color avia-section-default avia-no-border-styling  avia-bg-style-scroll  mfp-hide  container_wrap fullsize' style=' '  ><div class='container' ><div class='template-page content  av-content-full alpha units'><div class='post-entry post-entry-type-page post-entry-58609'><div class='entry-content-wrapper clearfix'>\n<div class=\"flex_column av_one_fourth  flex_column_div av-zero-column-padding first  \" style='border-radius:0px; '><div  class='avia-image-container  av-styling-    avia-align-center '  itemprop=\"image\" itemscope=\"itemscope\" itemtype=\"https:\/\/schema.org\/ImageObject\"  ><div class='avia-image-container-inner'><div class='avia-image-overlay-wrap'><img decoding=\"async\" class='wp-image-58303 avia-img-lazy-loading-not-58303 avia_image' src=\"https:\/\/silvaco.com\/wp-content\/uploads\/2024\/11\/Lado_Filipovic-244x300.jpg\" alt='' title='Lado_Filipovic' height=\"300\" width=\"244\"  itemprop=\"thumbnailUrl\" srcset=\"https:\/\/silvaco.com\/wp-content\/uploads\/2024\/11\/Lado_Filipovic-244x300.jpg 244w, https:\/\/silvaco.com\/wp-content\/uploads\/2024\/11\/Lado_Filipovic-30x37.jpg 30w, https:\/\/silvaco.com\/wp-content\/uploads\/2024\/11\/Lado_Filipovic-45x55.jpg 45w, https:\/\/silvaco.com\/wp-content\/uploads\/2024\/11\/Lado_Filipovic-39x48.jpg 39w, https:\/\/silvaco.com\/wp-content\/uploads\/2024\/11\/Lado_Filipovic.jpg 390w\" sizes=\"(max-width: 244px) 100vw, 244px\" \/><\/div><\/div><\/div><\/div><div class=\"flex_column av_three_fourth  flex_column_div av-zero-column-padding   \" style='border-radius:0px; '><section class=\"av_textblock_section \"  itemscope=\"itemscope\" itemtype=\"https:\/\/schema.org\/CreativeWork\" ><div class='avia_textblock  '   itemprop=\"text\" ><h1>Machine Learning for Multi-Scale Plasma Process Integration and Optimization<\/h1>\n<h3>Abstract:<\/h3>\n<p>This talk will explore advancements in plasma etching process optimization for process technology computer-aided design (TCAD), focusing on the integration of multi-scale modeling with AI-driven techniques. Key topics will include the development of equipment-informed feature-scale models, utilizing machine learning (ML) to bridge the gap between reactor and feature scales in plasma chambers. This approach supports predictive modeling for high-aspect-ratio (HAR) structures, critical for complementary metal-oxide-semiconductor (CMOS) applications and emerging device architectures.<\/p>\n<p>A primary challenge in optimizing plasma etching processes is synchronizing the complex plasma chamber conditions across scales. We will discuss recent progress in creating surrogate models using equipment simulations such as the Hybrid Plasma Equipment Model (HPEM). Machine learning-based surrogate models, combined with available experimental data, can assist in an efficient generation of flux predictions. These models facilitate rapid feature-scale adjustments, fostering a digital twin environment with the potential for real-time optimization.<\/p>\n<p>Ultimately, the proposed workflows have the potential to merge complex plasma chamber environments to TCAD, significantly reducing reliance on trial-and-error experimentation. This could lead to a more streamlined, efficient, and greener semiconductor manufacturing process.<\/p>\n<h3>Speaker:<\/h3>\n<p><strong>Dr. Lado Filipovic<\/strong><br \/>\n<strong>Associate Professor and the Director of the Silvaco-supported Christian Doppler Laboratory for Multi-Scale Process Modeling of Semiconductor Devices and Sensors at the Institute for Microelectronics, TU Wien<\/strong><\/p>\n<p>Lado Filipovic is an Associate Professor and the Director of the Silvaco-supported Christian Doppler Laboratory for Multi-Scale Process Modeling of Semiconductor Devices and Sensors at the Institute for Microelectronics, TU Wien. His research focuses on advanced process modeling, technology computer-aided design (TCAD), and integrated semiconductor sensors. Dr. Filipovic obtained his habilitation in Semiconductor Based Integrated Sensors and his doctoral degree in Microelectronics from TU Wien in 2020 and 2012, respectively.<\/p>\n<p>Dr. Filipovic leads a diverse portfolio of research projects covering the full spectrum of technology readiness levels (TRLs), supported by the Austrian Science Fund (FWF), the Christian Doppler Research Association (CDG), the Austrian Research Promotion Agency (FFG), and the European Union, as well as through direct industry collaborations. A Senior Member of IEEE, Dr. Filipovic actively serves on Technical Program Committees for prominent IEEE conferences such as IEDM and SISPAD. His group has also released several open-source tools, including the process simulator ViennaPS, utilized by academia and industry for nanoelectronic device studies.<\/p>\n<p>Currently collaborating with industry partners like Silvaco, Fuji Electric, Infineon, as well as academic institutions worldwide (e.g., MIT, University of Glasgow, Arizona State University, Chinese Academy of Sciences), Dr. Filipovic\u2019s research delves into enabling multi-scale modeling of semiconductor device fabrication and operation. His group is also investigating the integration of van der Waals layered materials (2D materials), including graphene and MoS2, for advanced sensing applications.<\/p>\n<\/div><\/section><\/div>\n\n<\/div><\/div><\/div><!-- close content main div --><\/div><\/div><div id='christian_c'  class='avia-section main_color avia-section-default avia-no-border-styling  avia-bg-style-scroll  mfp-hide  container_wrap fullsize' style=' '  ><div class='container' ><div class='template-page content  av-content-full alpha units'><div class='post-entry post-entry-type-page post-entry-58609'><div class='entry-content-wrapper clearfix'>\n<div class=\"flex_column av_one_fourth  flex_column_div av-zero-column-padding first  \" style='border-radius:0px; '><div  class='avia-image-container  av-styling-    avia-align-center '  itemprop=\"image\" itemscope=\"itemscope\" itemtype=\"https:\/\/schema.org\/ImageObject\"  ><div class='avia-image-container-inner'><div class='avia-image-overlay-wrap'><img decoding=\"async\" class='wp-image-58344 avia-img-lazy-loading-not-58344 avia_image' src=\"https:\/\/silvaco.com\/wp-content\/uploads\/2024\/11\/Christian_Caillat.jpg\" alt='' title='Christian_Caillat' height=\"180\" width=\"169\"  itemprop=\"thumbnailUrl\" srcset=\"https:\/\/silvaco.com\/wp-content\/uploads\/2024\/11\/Christian_Caillat.jpg 169w, https:\/\/silvaco.com\/wp-content\/uploads\/2024\/11\/Christian_Caillat-35x37.jpg 35w, https:\/\/silvaco.com\/wp-content\/uploads\/2024\/11\/Christian_Caillat-52x55.jpg 52w, https:\/\/silvaco.com\/wp-content\/uploads\/2024\/11\/Christian_Caillat-45x48.jpg 45w\" sizes=\"(max-width: 169px) 100vw, 169px\" \/><\/div><\/div><\/div><\/div><div class=\"flex_column av_three_fourth  flex_column_div av-zero-column-padding   \" style='border-radius:0px; '><section class=\"av_textblock_section \"  itemscope=\"itemscope\" itemtype=\"https:\/\/schema.org\/CreativeWork\" ><div class='avia_textblock  '   itemprop=\"text\" ><h1>Applying Artificial Intelligence in Fab Technology Co-Optimization<\/h1>\n<h3>Abstract:<\/h3>\n<p>The common approach to optimize a fabrication process involves process and fab engineers creating and setting up Design of Experiments (DoEs) using a trial-and-error approach.<\/p>\n<p>This approach often leads to costly iterations since wafer fabrication is both expensive and time-consuming. Typically, it can take weeks to months of experimentation, depending on what process parameters are not meeting their targets.<\/p>\n<p>A new approach already in production use today leverages artificial intelligence (AI) and machine learning (ML) to generate an accurate simplified model of a fabrication step.<br \/>\nSilvaco\u2019s FTCO Platform incorporates Machine Learning to accelerate semiconductor Digital Twin development. With Silvaco\u2019s platform you can input your fabrication data and TCAD data to start building out an ML model.<\/p>\n<p>This presentation will showcase this FTCO flow with examples to give you more insight into this flow and how you can apply it for you and your team\u2019s needs.<\/p>\n<h3>Speaker:<\/h3>\n<p><strong>Dr. Christian Caillat<\/strong><br \/>\n<strong>Senior Staff CAE, Silvaco<\/strong><\/p>\n<p>Bio Dr. Christian Caillat is a Senior Staff CAE at Silvaco, based in Boise, ID. Prior to joining Silvaco in June 2023, he was with Micron Technology for 13 years, where he contributed to various projects over the years, including emerging memory program collaboration with imec, 3DNAND Cell team lead, advanced memory modeling.<\/p>\n<p>Dr Caillat holds an engineering degree in Electronics and a PhD in Microelectronics from the National Polytechnical Institute of Grenoble (France).<\/p>\n<\/div><\/section><\/div>\n\n<\/div><\/div><\/div><!-- close content main div --><\/div><\/div><div id='stefania_c'  class='avia-section main_color avia-section-default avia-no-border-styling  avia-bg-style-scroll  mfp-hide  container_wrap fullsize' style=' '  ><div class='container' ><div class='template-page content  av-content-full alpha units'><div class='post-entry post-entry-type-page post-entry-58609'><div class='entry-content-wrapper clearfix'>\n<div class=\"flex_column av_one_fourth  flex_column_div av-zero-column-padding first  \" style='border-radius:0px; '><div  class='avia-image-container  av-styling-    avia-align-center '  itemprop=\"image\" itemscope=\"itemscope\" itemtype=\"https:\/\/schema.org\/ImageObject\"  ><div class='avia-image-container-inner'><div class='avia-image-overlay-wrap'><img decoding=\"async\" class='wp-image-58557 avia-img-lazy-loading-not-58557 avia_image' src=\"https:\/\/silvaco.com\/wp-content\/uploads\/2024\/11\/Stefania_Carapezzi-1-236x300.jpg\" alt='' title='Stefania_Carapezzi' height=\"300\" width=\"236\"  itemprop=\"thumbnailUrl\" srcset=\"https:\/\/silvaco.com\/wp-content\/uploads\/2024\/11\/Stefania_Carapezzi-1-236x300.jpg 236w, https:\/\/silvaco.com\/wp-content\/uploads\/2024\/11\/Stefania_Carapezzi-1-29x37.jpg 29w, https:\/\/silvaco.com\/wp-content\/uploads\/2024\/11\/Stefania_Carapezzi-1-43x55.jpg 43w, https:\/\/silvaco.com\/wp-content\/uploads\/2024\/11\/Stefania_Carapezzi-1-38x48.jpg 38w, https:\/\/silvaco.com\/wp-content\/uploads\/2024\/11\/Stefania_Carapezzi-1.jpg 257w\" sizes=\"(max-width: 236px) 100vw, 236px\" \/><\/div><\/div><\/div><\/div><div class=\"flex_column av_three_fourth  flex_column_div av-zero-column-padding   \" style='border-radius:0px; '><section class=\"av_textblock_section \"  itemscope=\"itemscope\" itemtype=\"https:\/\/schema.org\/CreativeWork\" ><div class='avia_textblock  '   itemprop=\"text\" ><h1>How to Utilize Victory Analytics and Machine Learning to Calibrate TCAD Data<\/h1>\n<h3>Abstract:<\/h3>\n<p>Physics-based design using technology computer-aided design (TCAD) has provided fundamental contributions to R&amp;D in the semiconductor industry. Traditionally, TCAD modeling is mostly developed manually by expert designers using a trial-and-error procedure. However, the imperative acceleration of time-to-market to reduce development expenses calls for renovation of these conventional TCAD approaches.<\/p>\n<p>Machine learning (ML) \/ artificial intelligence (AI) techniques are currently considered to be essential enhancements for TCAD strategies. Silvaco, a prominent provider of TCAD, EDA software, and SIP solutions used to enable semiconductor design, is at the forefront in developing AI-powered TCAD.<\/p>\n<p>In this webinar, an ML-TCAD combined strategy is presented to boost the calibration of TCAD parameters to benchmark TCAD simulations against experimental data. This is achieved through a seamless flow between two of the latest tools from the Victory suite: Victory Design Of Experiment (DOE) and Victory Analytics.<\/p>\n<p>VDOE is a powerful project manager for efficiently running DOE with TCAD simulations. This essential step allows users to collect the TCAD outputs to be fed into Victory Analytics. Then, Victory Analytics uses ML-modelling to optimize TCAD parameters to fit the experimental data. Calibration of TCAD parameters of AlGaN\/GaN HEMT will be used to showcase this procedure as a case study.<\/p>\n<h3>Speaker:<\/h3>\n<p><strong>Dr. Stefania Carapezzi<\/strong><br \/>\n<strong>Field Applications Engineer, Silvaco<\/strong><\/p>\n<p>Dr. Stefania Carapezzi is currently a Field Applications Engineer at Silvaco France. She joined in March 2023. She obtained a PhD in Physics at University of Bologna, Italy, in 2014. Then, she was Post-Doc Researcher for several years at Advanced Research Center on Electronic System, Bologna, Italy and at LIRMM, University of Montpellier, CNRS, Montpellier, France. Her research work has been focused on TCAD simulation of Beyond CMOS devices and quantum effects in nanoscaled transistors.<\/p>\n<\/div><\/section><\/div>\n\n<\/div><\/div><\/div><!-- close content main div --><\/div><\/div><div id='david_g'  class='avia-section main_color avia-section-default avia-no-border-styling  avia-bg-style-scroll  mfp-hide  container_wrap fullsize' style=' '  ><div class='container' ><div class='template-page content  av-content-full alpha units'><div class='post-entry post-entry-type-page post-entry-58609'><div class='entry-content-wrapper clearfix'>\n<div class=\"flex_column av_one_fourth  flex_column_div av-zero-column-padding first  \" style='border-radius:0px; '><div  class='avia-image-container  av-styling-    avia-align-center '  itemprop=\"image\" itemscope=\"itemscope\" itemtype=\"https:\/\/schema.org\/ImageObject\"  ><div class='avia-image-container-inner'><div class='avia-image-overlay-wrap'><img decoding=\"async\" class='wp-image-18869 avia-img-lazy-loading-not-18869 avia_image' src=\"https:\/\/silvaco.com\/wp-content\/uploads\/2020\/02\/david_green1.jpg\" alt='' title='david_green[1]' height=\"100\" width=\"100\"  itemprop=\"thumbnailUrl\" srcset=\"https:\/\/silvaco.com\/wp-content\/uploads\/2020\/02\/david_green1.jpg 100w, https:\/\/silvaco.com\/wp-content\/uploads\/2020\/02\/david_green1-80x80.jpg 80w, https:\/\/silvaco.com\/wp-content\/uploads\/2020\/02\/david_green1-36x36.jpg 36w, https:\/\/silvaco.com\/wp-content\/uploads\/2020\/02\/david_green1-37x37.jpg 37w, https:\/\/silvaco.com\/wp-content\/uploads\/2020\/02\/david_green1-55x55.jpg 55w, https:\/\/silvaco.com\/wp-content\/uploads\/2020\/02\/david_green1-48x48.jpg 48w\" sizes=\"(max-width: 100px) 100vw, 100px\" \/><\/div><\/div><\/div><\/div><div class=\"flex_column av_three_fourth  flex_column_div av-zero-column-padding   \" style='border-radius:0px; '><section class=\"av_textblock_section \"  itemscope=\"itemscope\" itemtype=\"https:\/\/schema.org\/CreativeWork\" ><div class='avia_textblock  '   itemprop=\"text\" ><h1 class=\"p1\"><span class=\"s1\">Utilizing Physics-Based AI-Powered Digital Twins to Accelerate Design Optimization and Manufacturing Yield of SiC Power Devices<\/span><\/h1>\n<h3 class=\"p3\"><span class=\"s1\">Speaker:<\/span><\/h3>\n<p class=\"p3\"><strong><span class=\"s1\">Dr. David Green<br \/>\n<\/span><span class=\"s1\">Senior Field Applications Engineering, Silvaco<\/span><\/strong><\/p>\n<p class=\"p3\"><span class=\"s1\">Dr. David Green is a Senior Field Applications Engineering for Silvaco, based in Cambridge, UK. He has been with Silvaco for 18 years, with responsibilities including pre\/post sales support of TCAD customers in EMEA and development, as well as management of R &amp; D TCAD projects. He provides support on a wide variety of applications including power, display, reliability, and optical.<\/span><\/p>\n<p class=\"p3\"><span class=\"s1\">His PhD and subsequent post-doctoral work involved the design, simulation, development, and testing of vertical and lateral power devices for integrated circuits.<\/span><\/p>\n<\/div><\/section><\/div>\n\n<\/div><\/div><\/div><!-- close content main div --><\/div><\/div><div id='bogdan_t'  class='avia-section main_color avia-section-default avia-no-border-styling  avia-bg-style-scroll  mfp-hide  container_wrap fullsize' style=' '  ><div class='container' ><div class='template-page content  av-content-full alpha units'><div class='post-entry post-entry-type-page post-entry-58609'><div class='entry-content-wrapper clearfix'>\n<div class=\"flex_column av_one_fourth  flex_column_div av-zero-column-padding first  \" style='border-radius:0px; '><div  class='avia-image-container  av-styling-    avia-align-center '  itemprop=\"image\" itemscope=\"itemscope\" itemtype=\"https:\/\/schema.org\/ImageObject\"  ><div class='avia-image-container-inner'><div class='avia-image-overlay-wrap'><img decoding=\"async\" class='wp-image-18836 avia-img-lazy-loading-not-18836 avia_image' src=\"https:\/\/silvaco.com\/wp-content\/uploads\/2020\/02\/Bogdan-Tudor1-200x300.jpg\" alt='' title='Bogdan-Tudor[1]' height=\"300\" width=\"200\"  itemprop=\"thumbnailUrl\" srcset=\"https:\/\/silvaco.com\/wp-content\/uploads\/2020\/02\/Bogdan-Tudor1-200x300.jpg 200w, https:\/\/silvaco.com\/wp-content\/uploads\/2020\/02\/Bogdan-Tudor1-25x37.jpg 25w, https:\/\/silvaco.com\/wp-content\/uploads\/2020\/02\/Bogdan-Tudor1-37x55.jpg 37w, https:\/\/silvaco.com\/wp-content\/uploads\/2020\/02\/Bogdan-Tudor1-32x48.jpg 32w, https:\/\/silvaco.com\/wp-content\/uploads\/2020\/02\/Bogdan-Tudor1.jpg 381w\" sizes=\"(max-width: 200px) 100vw, 200px\" \/><\/div><\/div><\/div><\/div><div class=\"flex_column av_three_fourth  flex_column_div av-zero-column-padding   \" style='border-radius:0px; '><section class=\"av_textblock_section \"  itemscope=\"itemscope\" itemtype=\"https:\/\/schema.org\/CreativeWork\" ><div class='avia_textblock  '   itemprop=\"text\" ><h1>Power Devices SPICE Modeling with a Detailed SiC DMOS Parameter Extraction Methodology<\/h1>\n<h3>Abstract:<\/h3>\n<p>In this presentation, we start by introducing the SPICE modeling of power devices for different technologies including Si, GaN, and SiC, by using various methodologies such as compact models, Verilog-A and macromodels.<\/p>\n<p>Then, a significant portion of our presentation will be dedicated to illustrating the Spice modeling of a SiC DMOS in detail. The modeling flow will cover how to use the device I-V and C-V data, by also properly addressing its specific bias-dependent capacitances. Furthermore, we will exemplify how to deal with model tuning based on dynamic characteristics. Finally, we will also demonstrate how to also consider the dynamic temperature effects.<\/p>\n<h3>Speaker:<\/h3>\n<p><strong>Dr. Bogdan Tudor<\/strong><br \/>\n<strong>Head of Silvaco\u2019s Device Characterization Group<\/strong><\/p>\n<p>Dr. Bogdan Tudor is Head of Silvaco\u2019s Device Characterization Group. He is responsible for all aspects of the Device Characterization Group\u2019s activities, including R&amp;D, field operations and modeling services. He joined Silvaco in 2017. Prior to joining Silvaco, Dr. Tudor was a Principal Software Architect at ProPlus Design Solutions for 4 years and before that he was a Senior R&amp;D Engineer with Synopsys for 12 years. Dr. Tudor has an extensive expertise in Device characterization, Compact Model development, MOSFET Aging Reliability Analysis and Software development. Dr. Tudor holds a MS in Electrical Engineering and a Ph.D. in Microelectronics from the Polytechnic University in Bucharest, Romania.<\/p>\n<\/div><\/section><\/div>\n\n<\/div><\/div><\/div><!-- close content main div --><\/div><\/div><div id='eda_ip'  class='avia-section main_color avia-section-default avia-no-border-styling  avia-bg-style-scroll  mfp-hide  container_wrap fullsize' style=' '  ><div class='container' ><div class='template-page content  av-content-full alpha units'><div class='post-entry post-entry-type-page post-entry-58609'><div class='entry-content-wrapper clearfix'>\n<div class=\"flex_column av_one_fourth  flex_column_div av-zero-column-padding first  \" style='border-radius:0px; '><div  class='avia-image-container  av-styling-    avia-align-center '  itemprop=\"image\" itemscope=\"itemscope\" itemtype=\"https:\/\/schema.org\/ImageObject\"  ><div class='avia-image-container-inner'><div class='avia-image-overlay-wrap'><img decoding=\"async\" class='wp-image-53109 avia-img-lazy-loading-not-53109 avia_image' src=\"https:\/\/silvaco.com\/wp-content\/uploads\/2024\/01\/ben_1_web-210x300.png\" alt='Ben Louie' title='ben_1_web' height=\"300\" width=\"210\"  itemprop=\"thumbnailUrl\" srcset=\"https:\/\/silvaco.com\/wp-content\/uploads\/2024\/01\/ben_1_web-210x300.png 210w, https:\/\/silvaco.com\/wp-content\/uploads\/2024\/01\/ben_1_web-26x37.png 26w, https:\/\/silvaco.com\/wp-content\/uploads\/2024\/01\/ben_1_web-39x55.png 39w, https:\/\/silvaco.com\/wp-content\/uploads\/2024\/01\/ben_1_web-34x48.png 34w, https:\/\/silvaco.com\/wp-content\/uploads\/2024\/01\/ben_1_web.png 400w\" sizes=\"(max-width: 210px) 100vw, 210px\" \/><\/div><\/div><\/div><\/div><div class=\"flex_column av_three_fourth  flex_column_div av-zero-column-padding   \" style='border-radius:0px; '><section class=\"av_textblock_section \"  itemscope=\"itemscope\" itemtype=\"https:\/\/schema.org\/CreativeWork\" ><div class='avia_textblock  '   itemprop=\"text\" ><h1>EDA and IP Updates<\/h1>\n<h3 class=\"p1\"><span class=\"s1\">Abstract:<\/span><\/h3>\n<p class=\"p2\"><span class=\"s1\">Ben Louie will provide an update on Silvaco\u2019s Analog Custom Design product portfolio, new features and functionality, and the future of Silvaco\u2019s EDA solutions.<\/span><\/p>\n<h3>Speakers:<\/h3>\n<p class=\"p1\"><strong><span class=\"s1\">Ben Louie<br \/>\n<\/span><span class=\"s1\">VP and GM of IP Business Unit &#8211; Silvaco<\/span><\/strong><\/p>\n<p class=\"p3\"><span class=\"s1\">Ben Louie is Vice President and General Manager of the IP Business Unit responsible for managing all semiconductor design IP. He has over 22 years of experience in Memory design encompassing NOR Flash, NAND Flash, and MRAM. Before joining Silvaco, Ben made significant contributions to semiconductor startups such as Spin Memory, Zeno Semiconductor, and MagSil. His expertise also extends to established industry players, having worked at Micron Technology and Xilinx. At Micron Technology, Ben led the Design team in the transition from NOR flash to NAND flash and was the design lead\/manager for their first NAND products. Ben holds a Bachelor of Science Degree in Electrical Engineering and a Master of Science Degree in Electrical Engineering from Santa Clara University. He has been issued 123 US Patents.<\/span><\/p>\n<\/div><\/section><\/div>\n\n<\/div><\/div><\/div><!-- close content main div --><\/div><\/div><div id='stefano_p'  class='avia-section main_color avia-section-default avia-no-border-styling  avia-bg-style-scroll  mfp-hide  container_wrap fullsize' style=' '  ><div class='container' ><div class='template-page content  av-content-full alpha units'><div class='post-entry post-entry-type-page post-entry-58609'><div class='entry-content-wrapper clearfix'>\n<div class=\"flex_column av_one_fourth  flex_column_div av-zero-column-padding first  \" style='border-radius:0px; '><div  class='avia-image-container  av-styling-    avia-align-center '  itemprop=\"image\" itemscope=\"itemscope\" itemtype=\"https:\/\/schema.org\/ImageObject\"  ><div class='avia-image-container-inner'><div class='avia-image-overlay-wrap'><img decoding=\"async\" class='wp-image-41421 avia-img-lazy-loading-not-41421 avia_image' src=\"https:\/\/silvaco.com\/wp-content\/uploads\/2022\/06\/StefanoP.jpg\" alt='Stefano Pettazzi' title='StefanoP' height=\"140\" width=\"140\"  itemprop=\"thumbnailUrl\" srcset=\"https:\/\/silvaco.com\/wp-content\/uploads\/2022\/06\/StefanoP.jpg 140w, https:\/\/silvaco.com\/wp-content\/uploads\/2022\/06\/StefanoP-80x80.jpg 80w, https:\/\/silvaco.com\/wp-content\/uploads\/2022\/06\/StefanoP-36x36.jpg 36w, https:\/\/silvaco.com\/wp-content\/uploads\/2022\/06\/StefanoP-37x37.jpg 37w, https:\/\/silvaco.com\/wp-content\/uploads\/2022\/06\/StefanoP-55x55.jpg 55w, https:\/\/silvaco.com\/wp-content\/uploads\/2022\/06\/StefanoP-48x48.jpg 48w\" sizes=\"(max-width: 140px) 100vw, 140px\" \/><\/div><\/div><\/div><\/div><div class=\"flex_column av_three_fourth  flex_column_div av-zero-column-padding   \" style='border-radius:0px; '><section class=\"av_textblock_section \"  itemscope=\"itemscope\" itemtype=\"https:\/\/schema.org\/CreativeWork\" ><div class='avia_textblock  '   itemprop=\"text\" ><h1>EDA Solutions for Physical Design of Discrete Power Devices<\/h1>\n<h3>Abstract:<\/h3>\n<p>In discrete power device development, physical design and verification are essential for ensuring performance, reliability, and manufacturability. This presentation explores how Silvaco\u2019s Expert Layout Editor and SmartDRC streamline the physical design process, particularly for complex power device geometries, which often involve also numerous curved shapes. The session will highlight Expert\u2019s capabilities for efficient layout creation, as well as SmartDRC\u2019s high performance in verifying layouts with many curved geometries, commonly a challenging aspect for DRC (Design Rule Checking) engines, while ensuring both accuracy and speed. The integration of Silvaco\u2019s broader flow, combining TCAD and EDA, will also be briefly introduced, a unique offering in the market for power devices, allowing customers to rely on a single vendor for both aspects.<\/p>\n<h3>Speaker:<\/h3>\n<p><strong>Stefano Pettazzi<\/strong><br \/>\n<strong>Staff Applications Engineer, Silvaco, Inc.<\/strong><\/p>\n<p>Stefano Pettazzi holds an M.S. degree in Electrical and Electronics Engineering from the University of Pavia, Italy. With nearly 25 years of experience in EDA and microelectronics companies, he has been with Silvaco since 2012, serving as a Staff Applications Engineer, supporting EDA software for both front-end and back-end design flows.<\/p>\n<\/div><\/section><\/div>\n\n<\/div><\/div><\/div><!-- close content main div --><\/div><\/div><div id='jivaro'  class='avia-section main_color avia-section-default avia-no-border-styling  avia-bg-style-scroll  mfp-hide  container_wrap fullsize' style=' '  ><div class='container' ><div class='template-page content  av-content-full alpha units'><div class='post-entry post-entry-type-page post-entry-58609'><div class='entry-content-wrapper clearfix'>\n<div class=\"flex_column av_one_fourth  flex_column_div av-zero-column-padding first  \" style='border-radius:0px; '><div  class='avia-image-container  av-styling-    avia-align-center '  itemprop=\"image\" itemscope=\"itemscope\" itemtype=\"https:\/\/schema.org\/ImageObject\"  ><div class='avia-image-container-inner'><div class='avia-image-overlay-wrap'><img decoding=\"async\" class='wp-image-43300 avia-img-lazy-loading-not-43300 avia_image' src=\"https:\/\/silvaco.com\/wp-content\/uploads\/2022\/09\/Chung-Chun_Chen.jpg\" alt='Chung-Chun Chen' title='Chung-Chun_Chen' height=\"300\" width=\"210\"  itemprop=\"thumbnailUrl\" srcset=\"https:\/\/silvaco.com\/wp-content\/uploads\/2022\/09\/Chung-Chun_Chen.jpg 210w, https:\/\/silvaco.com\/wp-content\/uploads\/2022\/09\/Chung-Chun_Chen-26x37.jpg 26w, https:\/\/silvaco.com\/wp-content\/uploads\/2022\/09\/Chung-Chun_Chen-39x55.jpg 39w, https:\/\/silvaco.com\/wp-content\/uploads\/2022\/09\/Chung-Chun_Chen-34x48.jpg 34w\" sizes=\"(max-width: 210px) 100vw, 210px\" \/><\/div><\/div><\/div><\/div><div class=\"flex_column av_three_fourth  flex_column_div av-zero-column-padding   \" style='border-radius:0px; '><section class=\"av_textblock_section \"  itemscope=\"itemscope\" itemtype=\"https:\/\/schema.org\/CreativeWork\" ><div class='avia_textblock  '   itemprop=\"text\" ><h1>Jivaro Pro Advanced Parasitic Reduction<\/h1>\n<h3 class=\"p1\"><span class=\"s1\">Speaker:<\/span><\/h3>\n<p class=\"p2\"><span class=\"s2\"><b>Chung-Chun Chen, Director of Analog Design<\/b><\/span><span class=\"s1\"><b><br \/>\n<\/b><\/span><span class=\"s2\"><b>Silicon Creations\u00a0<\/b><\/span><\/p>\n<p class=\"p3\"><span class=\"s1\">Chung-Chun (CC) Chen has been with Silicon Creations since 2011 and is a principal circuit architect for SerDes IO interface. Currently, CC leads SerDes team as a Director of Analog\/Mixed-Signal Design at Silicon Creations in Atlanta, Georgia since being back in 2019. During 2018 \u2013 2019, CC joined Ubilinx Technology (Realtek Semiconductor Group) in San Jose, CA, and he was the driver\/architect of Realtek\u2019s high-speed Serdes technologies. During 2011 \u2013 2018, CC was a senior analog designer\/manager at Silicon Creations in Atlanta, Georgia while he designed analog IP products including Ring-based &amp; LC tank PLLs, Serializer, De-serializer with all clocking building blocks (PLL\/CDR, phase interpolator) and equalization (FFE, CTLE, DFE) circuitry. Before joining Silicon Creations, he was a research staff member at Samsung Electro-Mechanics design center in Atlanta, Georgia. Prior to this, he was a principal engineer at TSMC in Hsinchu, Taiwan, where he worked on clocking architecture design and related customer support.<\/span><\/p>\n<p class=\"p3\"><span class=\"s1\">Chung-Chun (CC) Chen (S\u201902\u2013M\u201909\u2013SM\u201917) was born in Taipei, Taiwan, in 1979. He received the M.S. and Ph.D. degrees in electrical engineering from National Taiwan University, Taipei, Taiwan, in 2004 and 2009, respectively. His current research interests focus on circuit designs in clocking and other SerDes building blocks for high-speed communication systems. He has published over 15 papers in peer-reviewed conferences and journals. He is a Senior Member of the IEEE and served as a reviewer of JSSC and T-MTT.<\/span><\/p>\n<\/div><\/section><\/div>\n\n<\/div><\/div><\/div><!-- close content main div --><\/div><\/div><div id='carlos_b'  class='avia-section main_color avia-section-default avia-no-border-styling  avia-bg-style-scroll  mfp-hide  container_wrap fullsize' style=' '  ><div class='container' ><div class='template-page content  av-content-full alpha units'><div class='post-entry post-entry-type-page post-entry-58609'><div class='entry-content-wrapper clearfix'>\n<div class=\"flex_column av_one_fourth  flex_column_div av-zero-column-padding first  \" style='border-radius:0px; '><div  class='avia-image-container  av-styling-    avia-align-center '  itemprop=\"image\" itemscope=\"itemscope\" itemtype=\"https:\/\/schema.org\/ImageObject\"  ><div class='avia-image-container-inner'><div class='avia-image-overlay-wrap'><img decoding=\"async\" class='wp-image-58308 avia-img-lazy-loading-not-58308 avia_image' src=\"https:\/\/silvaco.com\/wp-content\/uploads\/2024\/11\/Carlos_Berlitz.jpg\" alt='' title='Carlos_Berlitz' height=\"261\" width=\"217\"  itemprop=\"thumbnailUrl\" srcset=\"https:\/\/silvaco.com\/wp-content\/uploads\/2024\/11\/Carlos_Berlitz.jpg 217w, https:\/\/silvaco.com\/wp-content\/uploads\/2024\/11\/Carlos_Berlitz-31x37.jpg 31w, https:\/\/silvaco.com\/wp-content\/uploads\/2024\/11\/Carlos_Berlitz-46x55.jpg 46w, https:\/\/silvaco.com\/wp-content\/uploads\/2024\/11\/Carlos_Berlitz-40x48.jpg 40w\" sizes=\"(max-width: 217px) 100vw, 217px\" \/><\/div><\/div><\/div><\/div><div class=\"flex_column av_three_fourth  flex_column_div av-zero-column-padding   \" style='border-radius:0px; '><section class=\"av_textblock_section \"  itemscope=\"itemscope\" itemtype=\"https:\/\/schema.org\/CreativeWork\" ><div class='avia_textblock  '   itemprop=\"text\" ><h1>Using Viso to Investigate, Analyze and Solve Advanced Parasitics Issues<\/h1>\n<h3>Abstract:<\/h3>\n<p>In advanced technology nodes the impacts of parasitics in a design can be severe. Using simulations to identify and investigate such impact can be long and laborious. Viso is capable of tackling these issues and speed-up parasitics analysis. Viso is an advanced parasitics analysis solution to quickly analyze RC parasitic networks. Viso handles advanced nodes effortlessly, and its intuitive user interface allows to easily highlight and identify parasitics issues in the design. Viso features multiple analysis to obtain accurate information of the parasitics network, like timing estimations, crosstalk effects and matching between different nets. Such results can then be used to pinpoint troublesome areas in the design.<\/p>\n<p>Here we will demonstrate how Viso can be used to investigate RC parasitic issues in high-speed circuits without the need of multiple iterations of long simulations.<\/p>\n<h3>Speaker:<\/h3>\n<p><strong>Carlos Augusto Berlitz, PhD<\/strong><br \/>\n<strong>Corporate Application Engineer (CAE), Silvaco Inc.<\/strong><\/p>\n<p>Carlos Augusto Berlitz, PhD, is a Corporate Application Engineer for RC parasitics analysis and reduction EDA solutions at Silvaco. He is responsible for providing support, test and contribute to the roadmap of the EDA tools for RC parasitics analysis and reduction. He worked in circuit design and support in different companies. Dr. Berlitz joined Silvaco&#8217;s EDA team in 2023.<\/p>\n<p>He holds a PhD in Electronics, Electrotechnics, Automation and Signal Processing from INSA Lyon, France, an MS in Electrical Engineering from Grenoble Alpes University (UGA), France, and a BS in Electrical Engineering from Federal University of Rio Grande do Sul (UFRGS), Brazil.<\/p>\n<\/div><\/section><\/div>\n\n<\/div><\/div><\/div><!-- close content main div --><\/div><\/div><div id='siti_m'  class='avia-section main_color avia-section-default avia-no-border-styling  avia-bg-style-scroll  mfp-hide  container_wrap fullsize' style=' '  ><div class='container' ><div class='template-page content  av-content-full alpha units'><div class='post-entry post-entry-type-page post-entry-58609'><div class='entry-content-wrapper clearfix'>\n<div class=\"flex_column av_one_fourth  flex_column_div av-zero-column-padding first  \" style='border-radius:0px; '><div  class='avia-image-container  av-styling-    avia-align-center '  itemprop=\"image\" itemscope=\"itemscope\" itemtype=\"https:\/\/schema.org\/ImageObject\"  ><div class='avia-image-container-inner'><div class='avia-image-overlay-wrap'><img decoding=\"async\" class='wp-image-58312 avia-img-lazy-loading-not-58312 avia_image' src=\"https:\/\/silvaco.com\/wp-content\/uploads\/2024\/11\/Siti-Mariyam.jpg\" alt='' title='Siti Mariyam' height=\"280\" width=\"267\"  itemprop=\"thumbnailUrl\" srcset=\"https:\/\/silvaco.com\/wp-content\/uploads\/2024\/11\/Siti-Mariyam.jpg 267w, https:\/\/silvaco.com\/wp-content\/uploads\/2024\/11\/Siti-Mariyam-35x37.jpg 35w, https:\/\/silvaco.com\/wp-content\/uploads\/2024\/11\/Siti-Mariyam-52x55.jpg 52w, https:\/\/silvaco.com\/wp-content\/uploads\/2024\/11\/Siti-Mariyam-46x48.jpg 46w\" sizes=\"(max-width: 267px) 100vw, 267px\" \/><\/div><\/div><\/div><\/div><div class=\"flex_column av_three_fourth  flex_column_div av-zero-column-padding   \" style='border-radius:0px; '><section class=\"av_textblock_section \"  itemscope=\"itemscope\" itemtype=\"https:\/\/schema.org\/CreativeWork\" ><div class='avia_textblock  '   itemprop=\"text\" ><h1>Standard Cells Characterization Challenges and Improvement<\/h1>\n<h3>Abstract:<\/h3>\n<p>As an active semiconductor foundry, process or technology development and enhancement is frequent. To meet and verify the enhancement on library, library optimization and validation is needed. In this presentation, we share specific contributions of Silvaco tools in overcoming the current challenges during SilTerra\u2019s IP library development process in a unique, dynamic way to realize the optimization and validation, which ultimately results in reducing characterization timing.<\/p>\n<h3>Speaker:<\/h3>\n<p><strong>Siti Mariyam <\/strong><br \/>\n<strong>IP Senior Engineer, SilTerra Malaysia Sdn. Bhd <\/strong><\/p>\n<p>Education : Bachelor of Electronics System Engineering University of Technology Malaysia (UTM) , Malaysia<\/p>\n<p>Skill Set and Expertise : Standard Cells &amp; IO Library Development and Silicon Validation<\/p>\n<\/div><\/section><\/div>\n\n<\/div><\/div><\/div><!-- close content main div --><\/div><\/div><div id='fernando_c'  class='avia-section main_color avia-section-default avia-no-border-styling  avia-bg-style-scroll  mfp-hide  container_wrap fullsize' style=' '  ><div class='container' ><div class='template-page content  av-content-full alpha units'><div class='post-entry post-entry-type-page post-entry-58609'><div class='entry-content-wrapper clearfix'>\n<div class=\"flex_column av_one_fourth  flex_column_div av-zero-column-padding first  \" style='border-radius:0px; '><div  class='avia-image-container  av-styling-    avia-align-center '  itemprop=\"image\" itemscope=\"itemscope\" itemtype=\"https:\/\/schema.org\/ImageObject\"  ><div class='avia-image-container-inner'><div class='avia-image-overlay-wrap'><img decoding=\"async\" class='wp-image-58903 avia-img-lazy-loading-not-58903 avia_image' src=\"https:\/\/silvaco.com\/wp-content\/uploads\/2024\/12\/Fernando_Carrion2-230x300.jpg\" alt='' title='Fernando_Carrion2' height=\"300\" width=\"230\"  itemprop=\"thumbnailUrl\" srcset=\"https:\/\/silvaco.com\/wp-content\/uploads\/2024\/12\/Fernando_Carrion2-230x300.jpg 230w, https:\/\/silvaco.com\/wp-content\/uploads\/2024\/12\/Fernando_Carrion2-791x1030.jpg 791w, https:\/\/silvaco.com\/wp-content\/uploads\/2024\/12\/Fernando_Carrion2-768x1000.jpg 768w, https:\/\/silvaco.com\/wp-content\/uploads\/2024\/12\/Fernando_Carrion2-542x705.jpg 542w, https:\/\/silvaco.com\/wp-content\/uploads\/2024\/12\/Fernando_Carrion2-28x37.jpg 28w, https:\/\/silvaco.com\/wp-content\/uploads\/2024\/12\/Fernando_Carrion2-42x55.jpg 42w, https:\/\/silvaco.com\/wp-content\/uploads\/2024\/12\/Fernando_Carrion2-37x48.jpg 37w, https:\/\/silvaco.com\/wp-content\/uploads\/2024\/12\/Fernando_Carrion2.jpg 881w\" sizes=\"(max-width: 230px) 100vw, 230px\" \/><\/div><\/div><\/div><\/div><div class=\"flex_column av_three_fourth  flex_column_div av-zero-column-padding   \" style='border-radius:0px; '><section class=\"av_textblock_section \"  itemscope=\"itemscope\" itemtype=\"https:\/\/schema.org\/CreativeWork\" ><div class='avia_textblock  '   itemprop=\"text\" ><h1 class=\"p1\"><span class=\"s1\">Standard Cell Library IP in Advanced FinFET Nodes for Low Voltage Applications<\/span><\/h1>\n<h3>Abstract:<\/h3>\n<p>The transition to advanced FinFET technology nodes brings a new set of challenges and opportunities to digital circuit design, particularly for low-voltage applications. This presentation examines the unique characteristics and complexities of FinFETs at these nodes, with a focus on standard cell design and operation in low-voltage environments. We will explore the impact of these challenges on key metrics like area, timing, power, variability, and how they influence the design of standard cells optimized for ultra-low voltage functionality.<\/p>\n<p>Silvaco\u2019s portfolio of low-voltage standard cell libraries for advanced FinFET nodes is introduced as a comprehensive solution to meet rigorous power and performance demands. This portfolio includes specialized offerings such as multi-bit flip-flops, retention flip-flops, high fan-in cells with reduced transistor stacks, and an extensive Power Management Kit (PMK). Designed for efficiency and reliability under reduced supply voltages, these libraries leverage multi-threshold options to enable a tailored balance between performance and power consumption. This presentation provides a technical foundation for design engineers tackling the stringent requirements of advanced FinFET nodes in low-voltage applications.<\/p>\n<p>.<\/p>\n<h3>Speaker:<\/h3>\n<p><strong>Fernando Carrion<\/strong><br \/>\n<strong><span data-olk-copy-source=\"MessageBody\">Design Engineer<\/span>, Silvaco<\/strong><\/p>\n<p>Fernando Carrion is an electrical engineer graduated from The Federal University of Rio Grande do Sul (UFRGS) and an Analog Circuit Designer certified by the IC Brazil program. He is currently a Design Engineer at Silvaco, with over 4 years of experience in standard cell design and characterization.<\/p>\n<\/div><\/section><\/div>\n\n<\/div><\/div><\/div><!-- close content main div --><\/div><\/div><div id='felipe_b'  class='avia-section main_color avia-section-default avia-no-border-styling  avia-bg-style-scroll  mfp-hide  container_wrap fullsize' style=' '  ><div class='container' ><div class='template-page content  av-content-full alpha units'><div class='post-entry post-entry-type-page post-entry-58609'><div class='entry-content-wrapper clearfix'>\n<div class=\"flex_column av_one_fourth  flex_column_div av-zero-column-padding first  \" style='border-radius:0px; '><div  class='avia-image-container  av-styling-    avia-align-center '  itemprop=\"image\" itemscope=\"itemscope\" itemtype=\"https:\/\/schema.org\/ImageObject\"  ><div class='avia-image-container-inner'><div class='avia-image-overlay-wrap'><img decoding=\"async\" class='wp-image-58420 avia-img-lazy-loading-not-58420 avia_image' src=\"https:\/\/silvaco.com\/wp-content\/uploads\/2024\/11\/Felipe-300x300.jpg\" alt='' title='Felipe' height=\"300\" width=\"300\"  itemprop=\"thumbnailUrl\" srcset=\"https:\/\/silvaco.com\/wp-content\/uploads\/2024\/11\/Felipe-300x300.jpg 300w, https:\/\/silvaco.com\/wp-content\/uploads\/2024\/11\/Felipe-80x80.jpg 80w, https:\/\/silvaco.com\/wp-content\/uploads\/2024\/11\/Felipe-36x36.jpg 36w, https:\/\/silvaco.com\/wp-content\/uploads\/2024\/11\/Felipe-180x180.jpg 180w, https:\/\/silvaco.com\/wp-content\/uploads\/2024\/11\/Felipe-37x37.jpg 37w, https:\/\/silvaco.com\/wp-content\/uploads\/2024\/11\/Felipe-55x55.jpg 55w, https:\/\/silvaco.com\/wp-content\/uploads\/2024\/11\/Felipe-48x48.jpg 48w, https:\/\/silvaco.com\/wp-content\/uploads\/2024\/11\/Felipe.jpg 634w\" sizes=\"(max-width: 300px) 100vw, 300px\" \/><\/div><\/div><\/div><\/div><div class=\"flex_column av_three_fourth  flex_column_div av-zero-column-padding   \" style='border-radius:0px; '><section class=\"av_textblock_section \"  itemscope=\"itemscope\" itemtype=\"https:\/\/schema.org\/CreativeWork\" ><div class='avia_textblock  '   itemprop=\"text\" ><h1>Advanced Node Library Development with Cello FinFET<\/h1>\n<h3>Abstract:<\/h3>\n<p>Felipe will demonstrate how Cello FinFET streamlines library development for advanced nodes. We\u2019ll explore how to leverage existing libraries for new nodes and use automation to efficiently generate GDSII from CDL files. Attendees will gain practical insights into using Cello FinFET to accelerate library development and enhance productivity in advanced node design.<\/p>\n<h3>Speaker:<\/h3>\n<p><strong>Felipe Bortolon<\/strong><br \/>\n<strong>Standard Cell Library IP, Silvaco<\/strong><\/p>\n<p>Felipe Bortolon is the Engineering Manager for the standard cell layout automation framework \u2013 Cello. He holds a Computer Engineering degree from PUCRS and a MSc in Microelectronics from UFRGS, Brazil.<\/p>\n<\/div><\/section><\/div>\n\n<\/div><\/div><\/div><!-- close content main div --><\/div><\/div><div id='ahmad_shaikh'  class='avia-section main_color avia-section-default avia-no-border-styling  avia-bg-style-scroll  mfp-hide  container_wrap fullsize' style=' '  ><div class='container' ><div class='template-page content  av-content-full alpha units'><div class='post-entry post-entry-type-page post-entry-58609'><div class='entry-content-wrapper clearfix'>\n<div class=\"flex_column av_one_fourth  flex_column_div av-zero-column-padding first  \" style='border-radius:0px; '><p><div  class='avia-image-container  av-styling-    avia-align-center '  itemprop=\"image\" itemscope=\"itemscope\" itemtype=\"https:\/\/schema.org\/ImageObject\"  ><div class='avia-image-container-inner'><div class='avia-image-overlay-wrap'><img decoding=\"async\" class='wp-image-51436 avia-img-lazy-loading-not-51436 avia_image' src=\"https:\/\/silvaco.com\/wp-content\/uploads\/2023\/09\/ahmad_m_new.jpg\" alt='' title='ahmad_m_new' height=\"300\" width=\"210\"  itemprop=\"thumbnailUrl\" srcset=\"https:\/\/silvaco.com\/wp-content\/uploads\/2023\/09\/ahmad_m_new.jpg 210w, https:\/\/silvaco.com\/wp-content\/uploads\/2023\/09\/ahmad_m_new-26x37.jpg 26w, https:\/\/silvaco.com\/wp-content\/uploads\/2023\/09\/ahmad_m_new-39x55.jpg 39w, https:\/\/silvaco.com\/wp-content\/uploads\/2023\/09\/ahmad_m_new-34x48.jpg 34w\" sizes=\"(max-width: 210px) 100vw, 210px\" \/><\/div><\/div><\/div><br \/>\n<div  class='avia-image-container  av-styling-    avia-align-center '  itemprop=\"image\" itemscope=\"itemscope\" itemtype=\"https:\/\/schema.org\/ImageObject\"  ><div class='avia-image-container-inner'><div class='avia-image-overlay-wrap'><img decoding=\"async\" class='wp-image-51432 avia-img-lazy-loading-not-51432 avia_image' src=\"https:\/\/silvaco.com\/wp-content\/uploads\/2023\/09\/shaikh_s.jpg\" alt='Shaikh A Shams' title='shaikh_s' height=\"300\" width=\"210\"  itemprop=\"thumbnailUrl\" srcset=\"https:\/\/silvaco.com\/wp-content\/uploads\/2023\/09\/shaikh_s.jpg 210w, https:\/\/silvaco.com\/wp-content\/uploads\/2023\/09\/shaikh_s-26x37.jpg 26w, https:\/\/silvaco.com\/wp-content\/uploads\/2023\/09\/shaikh_s-39x55.jpg 39w, https:\/\/silvaco.com\/wp-content\/uploads\/2023\/09\/shaikh_s-34x48.jpg 34w\" sizes=\"(max-width: 210px) 100vw, 210px\" \/><\/div><\/div><\/div><\/p><\/div><div class=\"flex_column av_three_fourth  flex_column_div av-zero-column-padding   \" style='border-radius:0px; '><section class=\"av_textblock_section \"  itemscope=\"itemscope\" itemtype=\"https:\/\/schema.org\/CreativeWork\" ><div class='avia_textblock  '   itemprop=\"text\" ><h1>LDO and Bandgap References for Low Voltage Operation<\/h1>\n<h3>Abstract:<\/h3>\n<p>A capless LDO providing up to 30 mA load current has been designed in TSMC N3P 3nm FinFET process. The output voltage of the LDO is programmable from 0.45 V to 0.9 V with 50mV increments and an input voltage is 1.2V +\/- 10 %. Very good PSRR (&gt; 40 dB @ 1KHz and &gt; 29 dB @ 10 MHz) and load regulation (&lt; 18 mV undershoot\/overshoot for 1A\/ns load transient) across all PVT corners (temperatures ranging from -40\u00b0C to 125\u00b0C) were achieved with compact area (&lt; 3400 sq um).<\/p>\n<p>A Bandgap Voltage Reference is a voltage reference circuit widely used in integrated circuits producing an almost constant voltage, with very little fluctuations from variations of power supply, load, time, temperature and process. Silvaco developed low and higher voltage Bandgap voltage references delivering 0.45 V and 0.92 V respectively with only 1% variation across -45\u00b0C to 150\u00b0C. The circuits have been designed in the TSMC N3P 3nm FinFET technology.<\/p>\n<h3>Speakers:<\/h3>\n<p><strong>Speaker Name Ahmad S. Mazumder<\/strong><br \/>\n<strong>Director of Engineering, Silvaco<\/strong><\/p>\n<p>Ahmad S Mazumder is a Director of Engineering in the IP Division of Silvaco. He is responsible for Development &amp; Customer support in all Analog and Interface IPs. He is an Industry veteran on the development of High-Speed Memory &amp; Interface IPs and all sorts of analog IPs. He worked on cutting edge DDR, extreme High-speed SerDes, Interfaces, ESD, Quality &amp; Reliability for 28 years at various SOC companies \u2013 Intel, Broadcom, C-Cube Microsystems etc. He joined Silvaco\u2019s IP Engineering Division in 2019 and is Instrumental in growing Analog\/IP business at an accelerated rate.<br \/>\nAhmad S Mazumder holds an MS in VLSI Semiconductor Design from the City University of New York and BS in Electrical &amp; Electronics Engineering from Bangladesh University of Engineering and Technology.<\/p>\n<p><strong>Shaikh A Shams<\/strong><br \/>\n<strong>Staff Engineer, Silvaco<\/strong><\/p>\n<p>Shaikh A Shams is a Staff Engineer in the Analog\/Interface IP Division of Silvaco. He is responsible for developing Analog and Interface IPs at Silvaco. He worked on High-speed SerDes, Interfaces, Voltage Regulators, AMS Design and Verification for 22 years at different companies \u2013 Intel Corporation, Global Foundries and Dialog Semiconductor. He joined Silvaco\u2019s IP Engineering Division in 2020. Shaikh A Shams holds an MS in Electrical and Computer Engineering from the University of Arizona.<\/p>\n<\/div><\/section><\/div>\n\n<\/div><\/div><\/div><!-- close content main div --><\/div><\/div><div id='mauricio_b'  class='avia-section main_color avia-section-default avia-no-border-styling  avia-bg-style-scroll  mfp-hide  container_wrap fullsize' style=' '  ><div class='container' ><div class='template-page content  av-content-full alpha units'><div class='post-entry post-entry-type-page post-entry-58609'><div class='entry-content-wrapper clearfix'>\n<div class=\"flex_column av_one_fourth  flex_column_div av-zero-column-padding first  \" style='border-radius:0px; '><div  class='avia-image-container  av-styling-    avia-align-center '  itemprop=\"image\" itemscope=\"itemscope\" itemtype=\"https:\/\/schema.org\/ImageObject\"  ><div class='avia-image-container-inner'><div class='avia-image-overlay-wrap'><img decoding=\"async\" class='wp-image-58322 avia-img-lazy-loading-not-58322 avia_image' src=\"https:\/\/silvaco.com\/wp-content\/uploads\/2024\/11\/Mauricio_Brochi.jpg\" alt='' title='Mauricio_Brochi' height=\"141\" width=\"166\"  itemprop=\"thumbnailUrl\" srcset=\"https:\/\/silvaco.com\/wp-content\/uploads\/2024\/11\/Mauricio_Brochi.jpg 166w, https:\/\/silvaco.com\/wp-content\/uploads\/2024\/11\/Mauricio_Brochi-43x37.jpg 43w, https:\/\/silvaco.com\/wp-content\/uploads\/2024\/11\/Mauricio_Brochi-63x55.jpg 63w, https:\/\/silvaco.com\/wp-content\/uploads\/2024\/11\/Mauricio_Brochi-48x41.jpg 48w\" sizes=\"(max-width: 166px) 100vw, 166px\" \/><\/div><\/div><\/div><\/div><div class=\"flex_column av_three_fourth  flex_column_div av-zero-column-padding   \" style='border-radius:0px; '><section class=\"av_textblock_section \"  itemscope=\"itemscope\" itemtype=\"https:\/\/schema.org\/CreativeWork\" ><div class='avia_textblock  '   itemprop=\"text\" ><h1>CAN: A Historical Overview from Classic to XL<\/h1>\n<h3><strong>Abstract:<\/strong><\/h3>\n<p>This presentation provides an overview of the Controller Area Network (CAN) protocol and its evolution, culminating in CAN XL, which enhances efficiency and connects to Ethernet standards like 10BASE-T1, addressing the needs of modern automotive communication, including Software-Defined Vehicles. The evolution began in 1986 with the original CAN protocol, which featured non-destructive arbitration, allowing high-priority frames to access the bus while disconnecting faulty nodes to maintain communication integrity. Initially designed for automotive applications, CAN&#8217;s limitations in data throughput became clear with larger electronic control unit (ECU) data packages. In response, the CAN FD (Flexible Data-rate) protocol was introduced in 2011, supporting data rates up to 8 Mbps and a payload of 64 bytes. Finally, the third generation, CAN XL, enables a maximum payload of 2048 bytes at speeds up to 20 Mbps.<\/p>\n<h3>Speaker:<\/h3>\n<p><strong>Antonio Mauricio Brochi<\/strong><br \/>\n<strong>Director of Automotive IP, Silvaco<\/strong><\/p>\n<p>Bachelor\u2019s degree in electronic engineering by the University of Campinas, Sao Paulo, Brazil. More than 30 years\u2019 experience in SoC Systems and IP with focus on Automotive and Industrial applications. Worked for Motorola\/NXP participating in the development of Microcontroller Cores, CAN Controllers, Automotive Timers, Cryptographic Accelerators and Low Power Controller, among others<\/p>\n<\/div><\/section><\/div>\n\n","protected":false},"excerpt":{"rendered":"<p>SURGE (Silvaco UseRs Global Event)\u3068\u306f\u3001\u30b7\u30eb\u30d0\u30b3\u304c\u958b\u50ac\u3059\u308b\u30ef\u30fc\u30eb\u30c9\u30ef\u30a4\u30c9\u306e\u30a4\u30d9\u30f3\u30c8\u3067\u3059\u3002<br \/>\nSURGE\u306fTCAD\u3001EDA\u3001IP\u306e\u5404\u5206\u91ce\u306b\u304a\u3044\u3066\u3001\u65b0\u3057\u3044\u6280\u8853\u306b\u3064\u3044\u3066\u8b70\u8ad6\u3057\u3001\u30e6\u30fc\u30b6\u306e\u7d4c\u9a13\u3092\u5171\u6709\u3057\u3001\u5148\u9032\u7684\u306a\u534a\u5c0e\u4f53\u8a2d\u8a08\u306e\u305f\u3081\u306e\u9769\u65b0\u7684\u306a\u6280\u8853\u3092\u767a\u898b\u3059\u308b\u305f\u3081\u306e\u30a4\u30d9\u30f3\u30c8\u3067\u3059\u3002<\/p>\n","protected":false},"author":7,"featured_media":0,"parent":0,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"","meta":{"footnotes":""},"categories":[],"tags":[],"yoast_head":"<!-- This site is optimized with the Yoast SEO Premium plugin v24.0 (Yoast SEO v24.0) - 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