Simulation Standard

Guardian-Net Netlist Extractor: An Example of Specific Device Extraction Using XI-Scripts

3月 1, 2003

Guardian LVS from Silvaco is an efficient, reliable, and diverse package that brings the benefit of high-speed verification to PC-based test environments. Guardian netlist extractor, included with the Guardian suite, is a dynamic module that supports the high-speed extraction of a variety of devices, including MOS transistors, resistors, capacitors, and other standard devices.

Complex Parallel-Series Reduction

3月 1, 2003

Silvaco’s Guardian LVS tool compares two circuits that are defined by their netlists. The comparison is based strictly on the topological structure of these circuits. Topologically equivalent netlists are considered different, even if they are functionally equivalent. There are several techniques available for designing the same functionality by means of topologically different netlists. While it is impossible for the LVS tool to "know" about all these techniques, many are supported.

Expert Editor Settings and Layer Cleaning

3月 1, 2003

I generated some layers in Expert by DRC script run, and after that, derived layers can not be cleaned by "Tools\Derived Layers\Clean Derived Layers\ Whole Project", otherwise, derived layers generated by Maverick can be cleaned this way. How can I clean them all?

Two-Dimensional ATLAS Device Simulation of Pentacene Organic Thin-film Transistors

2月 1, 2003

Recent years has seen rapid acceleration in the research and development of organic thin film transistors (OTFTs) as key components for active matrix displays, radio frequency identification tags, and many other small scale integrated circuits. There are many advantages to OTFTs, such as the flexibility of the plastic fabrication substrate and the potential cost savings to manufacturers that adopt a solution process and/or ink-jet printing process.

Exact2: Interconnect Parasitic Capacitance Simulator

2月 1, 2003

Exact2 from Silvaco is a sophisticated, physically-based simulation tool for calculating semiconductor interconnect capacitance values. Its purpose is to build a capacitance coefficient database that is usable by any layout parasitic capacitance (LPE) tool.

Laser Simulation Encompassing Molar Fraction Variation via DevEdit

2月 1, 2003

This article addresses the creation of semiconductor laser double heterostructures, and the subsequent simulation of laser output with DevEdit from Silvaco. A laser consists of a gain medium sandwiched between two mirrors forming the laser cavity. This is necessary for effective laser operation because the round trip gain of the device, including the material and mirror losses, is unity. In addition, there is an integer number of half-wavelengths of light inside the optical length of the laser cavity.