Parasitic Resistor Extraction with HIPEX-R


Layout parasitic extraction (LPE) plays an important role in post-layout verification process. Verification of the full chip layout is increasingly becoming a problem because sizes of IC layouts continue to grow due to new IC technologies. The complexity of IC design is demanding to consider the effects caused by parasitic capacitors and resistors. Parasitic devices are responsible for effects such as time delay, voltage drop, and signal integrity violation, that lead to low chip performance.

HIPEX-R is part of HIPEX software package for physical verification of multimillion transistor designs. It is a hierarchical full chip parasitic resistance extraction tool.