The full text for most of these papers may be found at the IEEE website at www.ieee.org.
Daewoong Kang, Hyungcheol Shin,
“Improving the cell characteristics using arch-active profile in NAND flash memory having 60 nm design-rule”,
Solid-State Electronics, Vol. 54, Issue 11, November 2010, pp. 1263-1268.
Seongjae Cho, Jung-Dal Choi, Byung-Gook Park, Il Hwan Cho,
“Effects of channel doping concentration and fin dimension variation on self-boosting of channel potential in NAND-type SONOS flash memory array based on bulk-FinFETs”,
Current Applied Physics, Vol. 10, Issue 4, July 2010, pp. 1096-1102.
M.A. Garcia-Ramirez, Yoshishige Tsuchiya, Hiroshi Mizuta,
“Hybrid circuit analysis of a suspended gate silicon nanodot memory (SGSNM) cell”,
Microelectronic Engineering, Vol. 87, Issues 5-8, May-August 2010, pp. 1284-1286.
Kyoung-Rok Han, Min-Kyu Jeong, Ilwhan Cho, Jong-Ho Lee,
“5-bit/cell Characteristics using mixed program/erase mechanism in recessed channel non-volatile memory cells”,
Current Applied Physics, Vol. 10, Issue 1, Supplement 1, January 2010, pp. e2-e4.
A. Abdul Aziz, N. Soin,
“Dependency of threshold voltage on floating gate and inter-polysilicon dielectric thickness for nonvolatile memory devices”,
2010 IEEE International Conference on Semiconductor Electronics (ICSE), 2010, pp. 83&87.
A. Yesayan, N. Chevillon, F. Prégaldiny, C. Lallement,
“Compact physics-based model for ultrashort FinFETs”,
2010 Proceedings of the 17th International Conference Mixed Design of Integrated Circuits and Systems (MIXDES), 2010, pp. 75&80.
Seongjae Cho, Jung Hoon Lee, Shinichi O’uchi, Kazuhiko Endo, Meishoku Masahara, Byung-Gook Park,
“Design of SOI FinFET on 32 nm technology node for low standby power (LSTP) operation considering gate-induced drain leakage (GIDL)”,
Solid-State Electronics, Vol. 54, Issue 10, October 2010, pp. 1060-1065.
M. Moreau, D. Munteanu, J.L. Autran,
“Simulation study of Short-Channel Effects and quantum confinement in double-gate FinFET devices with high-mobility materials”,
Microelectronic Engineering, In Press, Corrected Proof, Available online 6 September 2010.
M.A. Pavanello, J.A. Martino, E. Simoen, C. Claeys,
“Cryogenic operation of FinFETs aiming at analog applications”,
Cryogenics, Vol. 49, Issue 11, November 2009, pp. 590-594.
Yoon Kim, Seongjae Cho, Gil Sung Lee, Il Han Park, Jong Duk Lee, Hyungcheol Shin, Byung-Gook Park,
“3-dimensional terraced NAND (3D TNAND) flash memory-stacked version of folded NAND array”,
IEICE Transactions on Electronics, Vol. E92-C, Issue 5, May 2009, pp. 653-658.
Shin-ichi O’uchi, Kazuhiko Endo, Meishoku Masahara, Kunihiro Sakamoto, Yongxun Liu, Takashi Matsukawa, Toshihiro Sekigawa, Hanpei Koike, Eiichi Suzuki,
“Flex-pass-gate SRAM for static noise margin enhancement using FinFET-based technology”,
Solid-State Electronics, Vol. 52, Issue 11, November 2008, pp. 1694-1702.
Jang-Gn Yun, Yoon Kim, Il Han Park, Jung Hoon Lee, Sangwoo Kang, Dong-Hua Lee, Seongjae Cho, Doo-Hyun Kim, Gil Sung Lee, Won-Bo Sim, Younghwan Son, Hyungcheol Shin, Jong Duk Lee, Byung-Gook Park,
“Fabrication and characterization of fin SONOS flash memory with separated double-gate structure”,
Solid-State Electronics, Vol. 52, Issue 10, October 2008, pp. 1498-1504.
Mohammad Gh. Mohammad, Kewal K. Saluja,
“Analysis and test procedures for NOR flash memory defects”,
Microelectronics Reliability, Vol. 48, Issue 5, May 2008, pp. 698-709.
P. Magnone, V. Subramanian, B. Parvais, A. Mercha, C. Pace, M. Dehan, S. Decoutere, G. Groeseneken, F. Crupi, S. Pierro,
“Gate Vol.tage and geometry dependence of the series resistance and of the carrier mobility in FinFET devices”,
Microelectronic Engineering, Vol. 85, Issue 8, August 2008, pp. 1728-1731.
A. Kranti, et.al.,
“Optimizing FinFET geometry and parasitics for RF applications”,
IEEE International SOI Conference, 2008, pp.123-124, Oct. 2008.
Ismail Saad, Razali Ismail,
“Self-aligned vertical double-gate MOSFET (VDGM) with the oblique rotating ion implantation (ORI) method”,
Microelectronics Journal, In Press, Corrected Proof, Available online 7 May 2008.
L. Perniola, J. Razafi ndramora, P. Scheiblin, F. Daug´e, C. Jahan, B. De Salvo, G. Reimbold, F. Boulanger,
“A Semi-Analytical Model for the Subthreshold Behavior of FinFLASH Structures”,
CEA-LETI 17, Rue des Martyrs, F&38054, Grenoble, France, email@example.com
G. Ghibaudo INP Grenoble MINATEC 3, Parvis Louis N´eel, BP 257, 38016 Grenoble Cedex 1
S. Jacob 1, 2, L. Perniola1, P. Scheiblin1, B. De Salvo1, G. Lecarval1, E. Jalaguier1, G. Festes2, R. Coppard2, F. Boulanger1, S. Deleonibus1,
“TCAD Modeling and Data of NOR Nanocrystal Memories”,
1CEA-LETI, 17 rue des Martyrs, 38054 Grenoble Cedex 9, France, firstname.lastname@example.org
2ATMEL Rousset, Zone industrielle, 13790 Rousset, France
A. Kranti et al.,
“Significance of gate underlap architecture in FinFETs for low–Vol.tage Analog/RF applications”,
211th Electrochemical Society Meeting (Chicago, USA), In Proc. ECS Transactions (SOI Device Technology), Vol. 6, Issue 4, pp. 375-380, 2007.
J. Yu, K. Aflatooni,
“Leakage current in DRAM memory cell”,
2006 16th Biennial University / Goverment / Industry Microelectronics Symposium, 2007, pp. 191-194.
Byung-Kil Choi, Kyoung-Rok Han, Young Min Kim, Young June Park, Jong-Ho Lee,
“Threshold-Voltage Modeling of Body-Tied FinFETs (Bulk FinFETs) Electron Devices”
IEEE Transactions on Vol. 54, Issue 3, March 2007 pp. 537&545.
A. Kranti et al.,
“Comparative analysis of nanoscale MOS device architectures for RF applications”,
Semiconductor Science and Technology, Vol. 22, No. 5, pp. 481-491, 2007.
Hiroaki Yamazaki, Hiroki Nakamura, Hiroshi Sakuraba, Fujio Masuoka,
“Analysis of the subthreshold characteristics for the FC-SGT flash memory cell”,
Electronics and Communications in Japan (Part II: Electronics), Vol. 89, Issue 8, August 2006, pp. 34-41.
Kuk-Hwan KIM, Hyunjin LEE, and Yang-Kyu CHOI,
“Novel Structures for a 2-Bit per Cell of Nonvolatile Memory Using an Asymmetric Double Gate”
IEICE Transaction on Electronics, Vol. E89-C, NO.5 MAY 2006.
A. Kranti et al.,
“Device design considerations for nanoscale double and triple gate FinFETs”,
In Proc. 2005 IEEE SOI Conference, Honolulu, Hawaii, USA, pp. 96-98, 2005.
R. Duane, M. F. Beug, A. Mathewson,
“Novel capacitance coupling coefficient measurement methodology for floating gate nonvolatile memory devices”
IEEE Electron Device Letters, Vol. 26, Issue 7, July 2005, pp. 507-509.
L. Perniola, S. Bernardini, G. Iannaccone, P. Masson, B. De Salvo, G. Ghibaudo, C. Gerardi,
“Analytical model of the effects of a nonuniform distribution of stored charge on the electrical characteristics of discrete-trap nonvolatile memories”
IEEE Transactions on Nanotechnology, Vol. 4, Issue 3, May 2005, pp. 360-368.
L. Perniola1,2*, S. Bernardini3, G. Iannaccone1, 6, B. De Salvo 4, G. Ghibaudo2, P. Masson3, C. Gerardi5,
“Electrostatic Effect of Localized Charge in Dual Bit Memory Cells with DiscreteTraps”,
1Dipartimento di Ingegneria dell’Informazione, Università degli Studi di Pisa, Via Caruso, 56122 Pisa, Italy, *email@example.com
2IMEP-CNRS/INPG, Avenue de Martyrs 32, 38016 Grenoble, France
3L2MP-Polytech – IMT Technopôle de Château Gombert, 13451 Marseille Cedex 20 France
4CEA-LETI, Avenue de Martyrs 16, 38054 Grenoble, France
5STMicroelectronics, Catania, Italy
6IEIIT-CNR, Via Caruso, 56122 Pisa, Italy.
A. Gorur-Seetharam, C. Lee, E. C. Kan,
“The effect of gate geometry on the charging characteristics of metal nanocrystal memories”
Materials Research Society Symposium&Proceedings, Vol. 789, 2003, pp. 71-76.
M. Hahad, P. Hopper,
“High performance semiconductor device simulation on shared memory parallel computers”
SISPAD Sept. 2-4, 1996 pp. 137 -138.
Chimoon Huang and Tahui Wang,
“Transient simulation of EPROM writing characteristics, with a novel hot electron injection model”
Solid-State Electronics, Vol. 38, Issue 2, February 1995, pp. 461-464.