Cello FinFET

Advanced Technology Node Layout Generation

Overview

Cello FinFET^TM extends Cello’s framework to tackle the rising challenges of standard cell library design in advanced and emerging technology nodes. By leveraging the strict constraints of sub-10nm nodes, it offers a solution to automatically generate GDSII layouts from transistor netlists. Cello FinFET provides designers with a framework for exploring and encoding power, performance, and area (PPA) metrics, accelerate library augmentation, and evaluating the impact of design rules and architectural modifications in the layout result. Additionally, Cello FinFET offers a comprehensive layout customization scripting interface using TCL, integration with third-party verification tools (DRC, LVS, and PEX) with minimal disruption, and flexibility to use within a layout editing flow.

Product Brief

Advanced Layout Automation Flow

Compatible with all design rules
Correct by construction
Supports both single and double-height cells

Cello FinFET Flow

Cello FinFET Flow

Key Features

Sub-10nm FinFET support
Integrated place and route engine creates correct by construction layout
Compatible with multi-patterning rules, cut rules, or any other complex FinFET processes rules
Advanced process technology, including context sensitive spacing and enclosure rules, preferred shape patterns, self-aligned double patterning (SADP) and support of local interconnect
Scalable parallel processing to improve throughput
Multiple layout options are created simultaneously
Integration with leading third-party DRC, LVS and LPE tools to ensure high-quality sign-off layouts and minimal disruption to existing flows
Flexible setup of process technologies and foundry design rules, enabling ultra-fast, DRC clean layout generation

Key Benefits

Significantly improves productivity
Eliminates or greatly reduces manual layout effort
Fast turnaround time, complete library in one day
Enables exploration of different dimensions (cell architecture, design rules, sizing strategy, different track heights, DFM rules)
Consistent layout
Reuse of schematics reduces design time
Automates PDK updates