Verification of an Compact Model for Organic Thin-Film-Transistors by Using MixedMode Creating an CMOS Inverter Circuit with TCAD Transistor Devices

Organic thin-film transistors (OTFTs) are promising devices for future low-cost electronics[1][2]. However, to enable the development of this technology, circuit design simulation is needed. TCAD with MixedMode approach provides a suitable route for the physics based simulation of these transistors within simple circuits. As circuits become more complicated, more devices are needed and the computing time increases significantly. Compact models describe the behavior of the device with only a few equations and thus the computing time is reduced to a viable magnitude. Such equations are written down in a Verilog-A format which can be used by most SPICE simulators.

Hints, Tips and Solutions – Movie and PDF Report Generation with the DeckBuild GUI

IntroductionIn this article we will emphasize two new features of the DeckBuild deck editing environment. These are the movie creation on the one hand and the creation of PDF reports on the other. The latest version of DeckBuild allows you to use recorded history points to prepare movies and PDF reports of a simulation flow. We will start by first illustrating the basic history creation and script execution mechanism, followed by pointing out the creation of movies. After that, we will demonstrate how to create a customized PDF report out of your simulation flow.

Process Variation, Alignment and BEOL Effects on Circuit Level Performance

As process nodes continue to shrink, the requirement for additional physics is gradually creeping into each stage of the design process. By way of illustration, TCAD simulations are becoming more atomistic in nature, SPICE models are becoming process-aware to take account of localized strain effects, and back or middle end of line (BEOL and MEOL) parasitics are moving from exclusively 2D rule based solutions to full 3D structure field solvers for numerous critical sections of the layout.

Touch Panel Capacitance Extraction in Hipex Full Chip Extraction Tool Using Stellar Field Solver

The previously standalone Stellar GUI based field solver tool for parasitic extraction is now integrated into Hipex (Silvaco’s full chip extraction tool) in Expert GUI. In Hipex, user can choose proper extraction method (including Steller solver) among different approaches. The GUI of Expert (Silvaco’s layout editor) has been extended to provide technology setup for Stellar mode of Hipex. Also, Expert provides full functional features of GDS drawing, editing and rule checking. As opposed to the Clever field solver based on adaptive meshing, Stellar can handle very large layout size with less memory and reduced runtime with acceptable accuracy (as compared to Clever). Clever, as very accurate adaptive meshing field solver, can be used as reference accuracy check when Stellar or rule based parasitic extraction method is performed in Hipex. In this article, we will review the basic interface of Hipex in Expert GUI using Stellar as a field solver to extract capacitance in touch panel example.

Dynamic Analysis of Liquid Crystal Pixels

We have demonstrated in previous articles the static electrical and optical simulation of LC cells [1][2]. The last piece of the function for a comprehensive analysis of an LC pixel is the capability of performing transient simulation. In this article, we will show the dynamic calculation of the LC director and the combination of electrical and optical simulation.

Hints, Tips and Solutions – Adding An Impurity to a Diffusion Model and Enable Diffusion of a New Impurity in a Specific Material

OBJECTIVEAdd an impurity (H) to a material (silicon) for a diffusion model (Fermi). The description below refers to Victory Process version 7.27.X.

3D Topography Simulation of SiC Epitaxial Growth Modeled by Diffusive Flux and Gibbs-Thomson Effect

One of wide bandgap semiconductors, SiC has been widely applied to the power devices, and then, the super-junction MOS transistor of SiC is being investigated to obtain higher performance for Ron and BV [1]. The super-junction structure is fabricated by trench filling with the epitaxial growth [2, 3].

An Empirical Composition Dependent Model of Dopant Diffusion Coefficients in Si, Si1-x Gex and Ge Material Systems

Previously published fast empirical models for diffusion coefficients in silicon-germanium (Si1-x Gex) [1][2] were not applicable to high germanium content x≥0.5 and hence did not properly extend towards germanium. For some dopants, diffusion coefficients become very small and hence this model cannot be applied to devices containing silicon-germanium with high germanium content or devices containing silicon, silicon-germanium and germanium

TCAD Simulation of Leakage Through Threading Dislocations in GaN-based pn-diodes

Gallium nitride (GaN)-based devices for power electronics show superior performance in comparison to silicon carbide and silicon-based devices [1]–[3]. The development of vertical devices, like pn-diodes and power HEMTs results in higher power density and voltage handling. One of the key parameters of this technology is the dislocation density. This is lower in free-standing GaN-on-GaN epitaxy than in heteroepitaxial GaN growth on different substrates like SiC or Si, but still has a density of 104-106 cm-2 [4]. The diode reverse leakage seems to be related to the dislocation density, and it can be modelled with a Poole-Frenkel or a hopping conduction mechanism [5]. The Poole-Frenkel model is already implemented in the trap-assisted tunnelling model in Silvaco Atlas [6]. For the leakage in threading dislocations a variable-range hopping (VRH) model has been implemented in the simulator, based on Ref. [7].

Hints, Tips and Solutions – DeckBuild Remote VM Setup

This document describes how to setup a virtual environment suitable for the deckbuild remote mode. The host system to consider shall be Windows (7 or 10). The goal is to use the windows version of the TCAD GUI tools TonyPlot and DeckBuild and to run any simulation (Victory, Athena, Clever) on a Linux Virtual Machine (VM).