New Improvements in TFT Models: Amorphous (Level=35) and Poly-Silicon (Level=36) TFT

New improvements have been added to Shur a-Si:H and Poly-Si Thin Film Transistors models. These enhancements include self-heating effect and a new charge conservation model.

BSIM4_U ( BSIM4 Universal Routine )

This routine is a multitarget/geometry routine used to extract all kind of characteristics. There is the possibility to trace three different targets. This routine is based on full SMU definition. This definition could be done for 3 different targets grouped together in 4 different setup. It means that 12 different bias conditions can be defined. One device is associated with one setup therefore with one, two or three targets.ApplicationThis routine is a multitarget/geometry routine used to extract all kind of characteristics. There is the possibility to trace three different targets. This routine is based on full SMU definition. This definition could be done for 3 different targets grouped together in 4 different setup. It means that 12 different bias conditions can be defined. One device is associated with one setup therefore with one, two or three targets.

Measure CJSWG (CJGATE) Capacitance using UTMOST III

For the UTMOST III versions greater than 17.2.0.R, the UTMOST users can measure the CJSWG (CJGATE) capacitance using the "CJ/CJSW" routine. The CJ/CJSW routine in MOS technology has been modified to measure the CJSWG (Peripheral portion of the junction capacitance under the gate) capacitance.

Cross-Sectional Viewer in Expert

Cross-Sectional Viewer is a tool within Expert to simulate the cross sectional view of ICs along an arbitrary drawn cut-line on the layout. Cross-sectional Viewer is a link between the layout and the resulting device. It allows the designer to examine cross-sections of the device being designed. Cross-sectional drawings are useful for understanding design rules, parasitic coupling and other design and fabrication problems.

Expert: Recent Improvements in Hierarchical Layout Inspection

The functionality of several features of Expert layout editor has been enhanced to deal with hierarchical layouts in more convenient ways.

Applicability of Distance Computation for Graphs to LVS Discrepancy Analysis

An important step in electronic circuit design is layout versus schematic verification (LVS)

Expert Hints, Tips, and Solutions: Object Scripting, Layer Color Palette, Big Measurements

Q: Often I need to measure big objects. It order to position the ruler precisely I must zoom in at one end, zoom out that zoom again in at the other end. Is it possible too make this operation more convenient? For example, can I start the measurement in one window and finish it in another one?

Yield Analysis and Performance Optimization Using FastBlaze and SPAYN

In previous Simulation Standard articles (Nov 97 & Nov 98) FastBlaze has been presented as a new, highly efficient approach to simulating advanced HEMTs and MESFETs. Conventional device simulators often suffer from slow execution times, leading to a trade off between mesh density and physical model complexity against CPU run time and convergence. This requires engineers to compromise accuracy to achieve a reasonable throughput.

New Model for Simulation of Exposure Process in Complex Nonplanar Resist-Substrate Structures

Predictive and efficient lithography simulation is an important component of the semiconductor industry efforts to develop the next generation of deep submicron technologies. Emerging technologies are based on elements with very small feature sizes and extremely complex and nonplanar topographies. Therefore lithography processing has to provide high resolution with large depth of focus. Simultaneously such effects as nonplanar reflections and notching as well as refractive index dependence on local absorbed dose are very critical for printing small mask elements using short wavelength radiation. This work presents a new approach for simulating the exposure process, which takes into account these effects in complex nonplanar resist-substrate structures.

Fast, Physical, Predictive and Calibrated Modeling of Ion Implantation

In a Research & Development environment, Technology Computer Aided Design (TCAD) is involved in the device optimization loop and requires efficient and predictive implantation modeling with frequent updating of the range of validity. For this purpose, semi-empirical models using statistical distributions are mainly chosen, because this kind of simulation is faster than the physically based Monte-Carlo (MC) approach. We propose a methodology which can be applied to ion implantation modeling with easy build-up, and which gives a predictive capability in the explored experimental domain.