エントリー - Graham Bell

Modification of BEM for Precise Capacitance Extraction

6月 1, 2002カテゴリ: /作成者:

It is well-known that parasitic effects are no longer negligible for modern integrated circuit technology. Among the most important parasitic effects limiting the chip performance are interconnect related problems like extensive signal delays and crosstalk. The main numeric problem is extraction of parasitic capacitance, because it is a more complicated task than resistance extraction. The latest codes use directly 3D electrostatic solvers for this purpose. But the disadvantage of such approach is prohibitively long solution time for the problem. So the simplest model of 3D structures, when layout is splitted to 2D small pieces, can be used when it is necessary to handle complete IC’s in a reasonable amount of time.

Advanced Layout Editing Using XI-scripts

6月 1, 2002カテゴリ: /作成者:

To provide uniform etching of metal, dummy metal rectangles can be placed over an unused area of the chip. The following script generates dummy layer with a full array of metal rectangles over the whole cell area. It calls DRC script which sizes the real metal layout up by 2 µm and subtracts it from the dummy layer. Then the dummy layer sized up and down to remove any slivers left over from the subtraction phase.

A Model for Boron T.E.D. in Silicon: Full Couplings of Dopant with Free and Clustered Interstitials

5月 1, 2002カテゴリ: /作成者:

In this contribution we present a model for transient enhanced diffusion of boron in silicon. This model is based on the usual pair diffusion mechanism including non-equilibrium reactions between the dopant and the free point defects, taking into account their various charge states. In addition to, and fully coupled with the dopant diffusion we model the growth and dissolution of the interstitials and boron interstitials clusters associated with the anneal of the self-interstitial supersaturation created by the implantation step. It is thus possible to simulate a rather large set of experimental conditions, from conventional predeposition steps, to RTA after low energy implantation.

Breakdown Analysis of a Body-Contacted Submicron High Electron Mobility Transistor

5月 1, 2002カテゴリ: /作成者:

Interest continues to grow in the development of high electron mobility transistor (HEMT) technologies for micrometer and millimeter wave power applications. A primary concern of device designers working with such technologies is the breakdown behavior in both the on- and off-states. As is the case for most field-effect transistors, reducing device dimensions results in a larger internal electric field near the drain-end of the device?s channel. The presence of such a field within the device can affect many areas of device performance including the breakdown characteristics.

ATLAS Simulation of a Schottky Contact

5月 1, 2002カテゴリ: /作成者:

ATLAS allows the user to define a contact with a number of different boundary conditions; ohmic, Schottky, current controlled, floating or reflecting. The Schottky contact boundary condition realizes that at the metal semiconductor interface a barrier exists due to the presence of interface states.

Verilog-A Release in SmartSpice

4月 1, 2002カテゴリ: /作成者:

We give in this article an introduction to the Verilog-A SmartSpice interface. This new feature in SmartSpice allows the user to write their own physical models in the Verilog-A language. The first section of the paper gives a brief overview of the Verilog-A language. The second presents the ease of use of simulating transistor models as well as digital circuits with the new Verilog-A SmartSpice interface.