エントリー - Gigi Boss

User Probes and Arbitrary Parameter Sweeps in Victory Device

One of the new features in Victory Device is the ability to add user managed parameters to a log file. This can be used when sweeping parameters (manually or in a Deckbuild loop), such as doping, stress, or layer thicknesses, to add the swept parameter to a log file. To do so, simply create a USER probe (with an optional name), and set the parameter USER on the MODELS statement to some value. This parameter (and value) will be added to the log file. The available user parameters are USER1, USER2, USER3, and USER4. The following shows a DeckBuild loop (go victoryd) to simulate the effect of varying STRESS_XX on the mobility.

Learn About Victory Visual, Silvaco’s New Graphical Visualization Solution for TCAD

2022年9月23日 | 2:00-2:30 JST
本ウェビナーでは、シルバコのTCAD可視化ツールの最新世代であるVictory Visualの機能を順を追って説明します。本ウェビナーは、Victory Visualの主要な機能を理解するためのハウツーガイドであると同時に、Victory AtomisticおよびVictory Mesh – Solid Modeling向けの機能についても簡単に紹介することを目的としています。これまでのシルバコTCADツールのユーザおよび新しいユーザの視点から、多くの質問を取り上げます。

Quantum Transport Simulation at Atomistic Accuracy of a Nanowire FET

The FET physical dimensions continue to shrink to five nm node and below, characterized by new types of architectures with nanosheet (NS) and nanowire (NW) shapes [3]. The present choice of material is made of Si, Ge, or SiGe alloy thanks to their high carrier concentrations. In compliment to III-V technology envisaged for a while, new 2D materials are also investigated (for example, the TMDs monolayers1). Such nanomaterials and nano-architectures require atomistic simulations for at least two crucial reasons: 1) bulk parameters like the effective masses and forbidden bandgap are no longer pertinent quantities, and 2) the wave nature of charge carriers becomes predominant for predicting transport characteristics including scattering events.

Learn How Victory Atomistic TCAD Solution Can Help You Succeed at Prototyping Atomistic Nanoscale Devices

2022年9月9日 | 2:00-2:30 JST
超微細電界効果トランジスタ(FET)技術は、5nmノード以下の最先端技術アーキテクチャを設計するために、原子スケールでのシミュレーションを必要としています。Victory Atomisticは、非平衡グリーン関数(NEGF)と最先端のバンド構造計算を組み合わせることで、汎用的で予測性の高い高速シミュレーションを可能にします。

2022 TCAD Baseline Release

New Features in the 2022 Baseline Release:

  • Section 1: Process Simulation – New Features in 2022 Baseline Release
  • Section 2: Device Simulation – New Features in 2022 Baseline Release
  • Section 3: Victory Mesh – New Features in 2022 Baseline Release
  • Section 4: Silver – New Features in 2022 Baseline Release

Learn How to Efficiently Achieve Accurate Experimental Etch Profiles in FinFET and Memory Applications with Victory TCAD Solution

2022年8月12日 | 2:00-2:30 JST
本ウェビナーでは、FinFETとメモリデバイスへの適用を例に、これらの幾何学エッチング・モデルを紹介します。フィンの形状制御や、非理想的なエッチング形状(ボーイング、ツイスト)、セルフ・アライン・プロセス(マルチパターニング)を実現する技術を紹介します。

Simulation of the High Temperature Performance of InGaN ‘Topping’ Cells

This work reports on the design of a high efficiency InGaN-based two junction (2J) tandem solar cell via numerical simulation, operating at high temperatures (450o C) and under 200 suns for application in a hybrid concentrating solar thermal (CST) system. To address the polarization and band-offset issues for GaN/InGaN heterojunction solar cells, band engineering techniques are employed. A simple interlayer is proposed at the hetero-interface rather than using an In composition grading layer, which is difficult to fabricate. The base absorber thickness and doping concentration have been optimized for 1J cell performance, and current matching was imposed on the series constrained 2J tandem cell design. The simulation results show that the crystalline quality (short recombination lifetime) of current nitride materials is a critical limiting factor the performance of the 2J cell design at high temperatures. The theoretical conversion efficiency of the best devices can be as high as ~21.8% at 450o C and 200X based on the assumed material parameters.

Learn How Silvaco Flow Helps Designing and Simulating Pixel Arrays in Flat Panel Displays and Detectors

2022年7月1日 | 2:00-2:30 JST
本ウェビナーでは、ディスプレイおよびディテクタの大手企業が、シルバコのツールの機能を活用して、回路図およびレイアウトの編集、最新の TFT技術で必要となる非常に正確なフィールド・ソルバ・ベースの寄生抽出、寄生RC素子のネットリストへのバックアノテーション、大規模なピクセル・アレイの高速かつ正確なSPICEシミュレーションを実現している事例をご紹介します。

Investigation of Self-Heating Effects in SOI MOSFETs with Silvaco Numerical Simulation

Self-heating effect may cause over-heated damage and degradation for silicon-on-insulator (SOI) devices, so numerical counting heat generated, and distribution can optimize the radio frequency integrated circuits (RFICs) applications. Both conventional and high resistivity, trap-rich SOI substrates are fabricated to investigate self-heating effects. There are two identical n channel metal-oxide-semiconductor-field-effect transistors (nMOSFETs) placed together to share a common source and the same active silicon region. One MOSFET is biased above threshold voltage and into saturation to heat-up the active region as a heater, and another device is biased into the sub-threshold regime to track the temperature changes as a localized thermometer. Compared to bulk single crystal silicon, the trap-rich SOI substrate consists of a high-defected polysilicon layer, which has introduced between the buried oxide layer and substrate. Due to the grain boundaries, the polysilicon layer has more phonon scattering and less value of thermal conductivity. However, based on the measurement results, two types of substrates SOI devices have similar performance for temperature increased. Therefore, a Silvaco numerical simulation has been issued to analysis the heat flow distribution within the devices and dissipation solution.