エントリー - Gigi Boss

Learn How to Use Victory Process TCAD Geometric Etch Models in FinFET and Memory Applications

2023年5月19日
本ウェビナーでは、FinFETおよびメモリ製造への応用を題材として、幾何学エッチング・モデルを紹介します。フィン形状や、非理想的なエッチング・プロファイル(ボーイング、ツイスト)、自己整合プロセス(マルチパターニング)を実現する技術を紹介します。

Simulation Framework for Device-packaging Co-design for Power Electronics

The past several years has seen a fast deployment of wide-bandgap power devices in fast chargers, electric vehicles, data centers and renewable energy processing. The performance of power devices is fast progressing towards their intrinsic material limit. As these devices can handle higher voltage and larger current density, packaging and thermal management will become the key limiting factor for exploiting their benefits in power electronic converters and systems.

Automatic Grid Refinement for Thin Material Layer Etching in Process TCAD Simulations

The utilization of thin material layers is common in modern semiconductor device fabrication. Subsequent etching steps require an accurate modeling of these thin layers. Although level-set based process TCAD simulations are capable of representing flat thin material layers with sub-grid accuracy, topographical changes during etching processes expose the low underlying grid resolution, which leads to detrimental artifacts.