エントリー - Gigi Boss

Automatic Grid Refinement for Thin Material Layer Etching in Process TCAD Simulations

The utilization of thin material layers is common in modern semiconductor device fabrication. Subsequent etching steps require an accurate modeling of these thin layers. Although level-set based process TCAD simulations are capable of representing flat thin material layers with sub-grid accuracy, topographical changes during etching processes expose the low underlying grid resolution, which leads to detrimental artifacts.

3D TCAD Simulation of Gallium Nitride Tri-gate Junction HEMT

The GaN high electron mobility transistor (HEMT) has been commercialized as a power device with performance superior to Si devices in the voltage classes from 15 V to 900 V [1]. Most of commercial enhancement-mode (E-mode) HEMTs comprise a planar p-GaN gate. Recently, 3-D gate stacks, such as FinFET and tri-gate structures, have been introduced to lateral GaN HEMTs. They can realize superior gate controllability and E-mode operation with a higher current on/off ratio and lower gated channel resistance [2].