Platinum and gold are widely used as an effective method to control lifetime in silicon-based devices [1, 2, 3]. Platinum and gold are introduced as recombination centers to improve switching performance. Thermal diffusion is primarily used as the common method to introduce platinum or gold dopants into silicon. There is interest to better understand how the processing conditions for Pt/Au diffusion can affect switching behavior. Control and shaping of the profile is critical to obtain optimum device performance. In this article, Silvaco Victory TCAD tools   are used to predict the effect of platinum on a PiN diode’s reverse recovery time (Trr). The simulated platinum profile from process simulation is automatically fed into the device simulator, and the relationship between platinum diffusion processing parameters and Trr is effortlessly studied.
作成者: Gigi Boss
でも、Gigi Boss さんは、なんと 236 件ものエントリーに貢献されたことを誇りに思いましょう。
エントリー - Gigi Boss
February 24, 2022 | 10:00 am – 10:30 am (PST)
This webinar will illustrate with some specific published examples of how device simulation can be a powerful tool to help explain complex performance limiting device instabilities in both RF and power devices.
2022/2/11 | 3:00 am – 3:30 am (JST)
本ウェビナーでは、FinFET スタンダード・セルのレイアウト設計における課題をいくつか取り上げ、シルバコの Celloを使用して、これらの問題に対処する方法を説明します。
2022/2/18 | 3:00 am – 3:30 am (JST)
Super-junction based devices are a key enabling technology for power devices. Adjacent columns of p and n-type doped material with optimized doping levels enables box-like electric fields, maximizing the breakdown voltage. As the doping of the columns is comparatively high, the on-state losses can be minimized.
Fabrication of such structures in SiC can be particularly challenging. Ideally the p and n-type columns will be uniformly doped. Fluctuations in doping can cause local electric field variation causing the breakdown voltage to be less than ideal. Super-junction structures can be conceived in a number of ways, but current schemes all present challenges  in SiC. The simplest method, as used with silicon is to use multiple implants and epitaxy steps. This is quite impractical with SiC due to the low diffusivity of dopants, requiring many sequential implantation steps. Trench etch and refill is an alternative scheme but provides its own challenges with regards to charge control and quality of the trench re-fill.
2022/1/28 | 3:00 am – 3:35 am (JST)
December 12, 2021
Abstract— Silvaco TCAD simulations are employed to identify relevant current carrying mechanisms in amorphous selenium (a-Se) based detectors, using parameters obtained from experimental data, density functional theory calculations, and in-house bulk Monte Carlo simulations. The steady-state dark current behaviors in various a-Se detectors are analyzed by identifying all relevant current conduction mechanisms (e.g., space-charge limited current, bulk thermal generation, Schottky emission, Poole-Frenkel activated mobility and hopping conduction), as well as “acceptor” and “donor” defect density of states located in the forbidden band gap of a-Se. The theoretical models are validated by comparing them with experimental steady-state dark current densities in avalanche and non-avalanche a-Se detectors.
Abstract— A Singular Point Source MOS (S-MOS) cell concept suitable for power MOS based devices is presented. The S-MOS differs from a standard Planar or Trench MOS cell in the manner by which the total channel width per device area is devised. The S-MOS single cell channel width is defined as the peripheral length of a line running approximately along the N++ source and P channel junction which is positioned on a gated trench side-wall. The length of the line is established from a singular point implant source for forming the N++ source region which geometrically corresponds to the shape of the N++/P junction. The N++ and PChannel profiles achieved are similar to those for a planar cell, but for the S-MOS, they are situated on a trench side-wall. The total device channel width will therefore depend on the total number of gated trench side-walls per chip. The S-MOS provides a unique approach for MOS cell layout designs and is applicable to different MOS based power devices. In this paper, the S-MOS is implemented on a 1200V IGBT by means of 3D-TCAD simulations while providing results highlighting the potential advantages with respect to the device static and dynamic performance.
Keywords – MOS cell, Insulated gate bipolar transistors.
Abstract—During the last few years, oxide-based ReRAM technology has attracted intense industrial and scientific research interest. Therefore, we have performed an in-depth computational study with a focus on data retention besides the resistive switching and the current run-away. Our newly developed comprehensive TCAD (Technology Computer Aided Design) model provides deep insight into the underlying microscopic processes and is validated against experimental data as an accurate and predictive simulation tool.
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