Q: When I do an extract, the generated layers are present in the layout. If I need to do layout modifications I find it very cumbersome to deal with the generated layers. Is there a way to turn-off all of the generated layers so that layout modifications can be done without them cluttering things?
Hipex-NET uses two techniques to calculate resistor values. First method of resistance extraction, which is usual for full chip netlist extractors and uses heuristic algorithms to recognize common shapes for which were obtained empirical formulas depending on geometry of resistor body and resistor terminals. Unfortunately, this method doesn’t cover the wide range of resistors and can handle only rectangular resistors, L-bends, and T-shaped resistive fragments. It also can be used to calculate resistance of snake and dog-bone shapes. We should also note that comparing to Maverick, Hipex-NET recognizes some new shapes as routine shapes for which resistance value can be calculated by the well-known formulas [1].
Introduction
Mercury cadmium telluride (HgCdTe) is a semiconductor material whose material properties are adjustable through altering its constitutive molar fractions. HgCdTe has found extensive use in optical detection, and in particular found wide use in infrared photodetectors over the past few decades. Applications in this area have been the main driving force for research on this material and for a good review see [1].
III-Nitrides have recently attracted attention as a promising material class for high-power, high-frequency microelectronic applications at elevated temperatures. They possess large band gaps, relatively small effective masses in the conduction band minimum, large offsets to the conduction band satellite valleys, and high polar optical phonon frequencies. The large band gaps provide high-breakdown field strengths, while the other basic physical properties result in high low-field mobilities and high saturation velocities.
We describe here two approaches to model the quantum effects that can no more be neglected in actual and future devices. These models are the Schrödinger-Poisson and Density-Gradient methods fully integrated in the device simulator ATLAS. Simulations based on such methods are compared to each other on electron concentration and C-V curves in a MOS-capacitor.
To illustrate the use of this statement to find depletion widths we have used the standard MOSFET example mos1ex01.in to first create the structure. Then the drain voltage was swept to 5V and a structure was saved at this bias. Figure 1 shows this structure and has plottted the junction and the depletion edges.
1. Introduction
The Exact analysis stage extracts the user-required information necessary for the respective parasitic capacitances by probing the Exact database. This is performed via script files written in LISA (Language for Interfacing Silvaco Applications). This article demonstrates a systematic approach for writing analysis script files.
Introduction
In response to high demand, device designers are developing silica microlenslets that offer efficient coupling between optical fiber bundles and arrays of photodetectors, LEDs, or VCSELs. Microlenslet design involves precise control of the surface curvature in order to place the focus in the optimal region.
A new parallelization method has been implemented into SmartSpice. Now .ALTERs can be destributed not only over several CPUs (by using -P option), but over a network of computers as well.
Remote .ALTER processing works the following way:
When it is invoked (by using -remote command line option), SmartSpice will read the input deck and check for .ALTER statements in it. If there are no .ALTER statements in the input deck, SmartSpice will just continue simulating the given netlist in batch mode. If .ALTERs are found, SmartSpice will extract parts of the netlist which form entire circuits and write out each circuit as separate files (.ALTER files). Resulting files containing one altered circuit each are named by adding the suffix -n to the composite basical netlist file name and have no extension. Number of produced files equals to the amount of .ALTER statements in the composite netlist plus one (deck without .ALTERs).
In all previous versions of SmartSpice the model code (BSIM, diode etc.) was included in the one executable (SmartSpice ). This means any updates to the model code would take a while to reach the customer because of the full SPICE functionality checks required before releasing a new SmartSpice version.