• Interface PHYs

Silvaco IP offers production-proven high-speed interface IP solutions for Samsung Foundry. Items marked AQ are AEC-Q100 qualified and ASIL assessed for automotive applications.

Protocol Features
Samsung Foundry
28nm
FD-SOI
14 nm
11 nm
10 nm
8 nm
7 nm
5 nm*
PCIe PCIe Gen 3, 8 Gbps
PDF AQ
PDF
PCIe Gen 3/4, 16 Gbps
PDF
PDF AQ PDF

AQ

DDR DDR3/4, 3.2 Gbps, 32/64-bit
AQ
PDF
AQ
LPDDR3/4, 4.3 Gbps, 16/32-bit
AQ
PDF
AQ
DDR/LPDDR3 Combo, 1.6 Gbps, 32-bit
PDF
LPDDR4/4X, 4.3 Gbps, 16/32-bit
PDF
PDF
PDF AQ
LPDDR4/4X/5, 5.5 Gbps, 16-bit
PDF
PDF AQ
LPDDR4/4X/5, 6.4 Gbps, 16-bit

AQ

HBM2e, 3.2 Gbps

AQ

MIPI M-PHY G3, 6.0 Gbps (UFS only)
PDF
PDF
PDF
AQ
M-PHY G4, 12.0 Gbps (UFS only)
AQ

AQ AQ

D-PHY V1.2, 2.1 Gbps
PDF
PDF
C-PHY D-PHY Combo V1.1 (2.5 Gbps) / V1.2 (2.5 Gbps)
AQ

C-PHY D-PHY Combo V1.1 (2.5 Gbps) / V2.0 (4.5 Gbps)
PDF
PDF AQ

AQ

SerDes SerDes 56 Gbps, 10/50G-KR, 100G-KR2/4, 200G-KR4
PDF

HDMI HDMI 2.0 Tx, 6.0 Gbps
PDF
USB / DisplayPort Combo USB 3.1 Gen 1 / DP Tx Combo, 5 Gbps / 5.4 Gbps
PDF
AQ

AQ

V-by-One Tx, 4 Gbps, 16 lanes
PDF
Rx, 4 Gbps, 8 lanes
PDF

*ASIL assessment is underway and scheduled to be completed.

Contact Silvaco if you need additional info on a specific IP or you do not see the IP product you require.

Resources

High speed Interface Design: Best Practices

What’s in the New MIPI Alliance I3C V1.1 Standard?

Videos

News

Blogs

Everything You Want to Know about Silvaco Foundation IP

Customers

Rick Lazansky
 Over the past two years, Silicon Catalyst has been working with key industry players to develop a complete ecosystem that economically and effectively supports the new wave of semiconductor startups that we are seeing today. Our Portfolio Companies have consistently been requesting IP as the critical element that we had not been able to deliver. Silvaco’s offering fulfills a real hole that has been impeding the success of these startups. We are glad to deliver this capability as we continue to build the semiconductor start up ecosystem. 
Srinath Anantharaman
 The integrated solution enables design teams to collaborate efficiently in a secure design environment when developing their IPs or SoCs either locally or across multiple design sites. It enables design teams to successfully tapeout their designs by mitigating the risk by sharing and using the correct version of the design data and IPs. 
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