• Hipex

Hipex Full-chip Rule-based RC Parasitic Extraction

Hipex-RC provides an accurate and fast solution for the extraction of parasitic capacitance and resistance from hierarchical layouts of analog, mixed-signal, memory IC and SoC designs. As part of Silvaco’s complete analog custom design flow, RC parasitic extraction together with DRC/LVs is tightly integrated with the Silvaco Expert layout editor.

Working from GDSII, cell netlists and rule-based technology files, Hipex-RC performs the parasitic extraction for either the full chip or selected nets or nodes, then back-annotates the schematic netlist with the exacted parasitics.

The device extraction capabilities of Hipex-RC allows the generation of hierarchical netlists that preserve the original layout hierarchy and supports a wide range of standard and parameterized user-defined devices. In addition it performs electrical rule checking (ERC) for shorts, opens and dangles.

Built for efficient parallelization on multi-processing servers, Hipex-RC is fast with efficient memory usage for large, full chip designs.


  • Performance of a fast 2D extractor with capacitance calculation near 3D accuracy
  • Fast analysis of user selected critical nets or layers without extracting the full-chip
  • Supports lumped RC, C only, R only, Coupled C and fully distributed RC extraction
  • Back-annotates the extracted netlist with schematic node names, parasitic resistances and capacitances
  • Accurate device extraction for non 45 and non 90 degrees devices and arbitrary shape resistors
  • Enables total per net capacitance and point-to-point resistance calculation by providing extracted parasitic RC in P2P format

Analog Custom Design Resources

Analog Simulation
Analog Custom Design & Analysis
SmartSpice Gateway
Model Generation
Guardian DRC
Utmost IV Guardian LVS
Parasitic Extraction
Gateway – Schematic Capture Jivaro– Parasitic Reduction for Fast, Accurate Simulation
Expert – Layout Editor Viso – Parasitic Analyzer and Debugger
Guardian – DRC/LVS/Net Physical Verification Belledonne – Layout Parastic Extraction Comparison
SmartSpice – Circuit Simulator VarMan – Statistical Variation and Yield Analyzer
SmartView – Waveform Analyzer VarMan XMA Option – Full-chip RAM Yield Analyzer
SmartSpice RadHard – Radiation Effects Circuit Simulator VarMan for Libraries – Library Statistical Functional Verification
SmartSpice Pro– FastSPICE Simulator Utmost IV– Device Characterization and SPICE Modeling
Hipex – Full-Chip Parasitic Extraction Utmost IV Quick-Start– Model extraction and Optimization Templates
InVar IR – Drop and Thermal Analysis TechModeler – Verilog-A Blackbox Device Modeling

Using SmartSpice Compact Models

TFT and OLED SPICE Modeling Using Utmost IV




SmartSpice Does It Smart

Machine Learning in Silvaco EDA Software


Kunihisa Ishii
 More customers will be able to use our six-inch silicon foundry with our new 0.35 µm CMOS PDK for Silvaco custom design tools. With our partnership with Silvaco, who have a lot of experience in analog custom design solutions, we will reduce total development costs for our customers and extend our flexible foundry services. 
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