soiex13.in : 3D PD-SOI MOSFET Analysis for RF CMOS Applications
Requires: Victory Process - Victory Device
Minimum Versions: Victory Process 7.30.4.R, Victory Mesh 1.4.6.R, Victory Device 1.14.1.R
By default Victory Process and Device run on just one processor. To ensure better performance on your computer, the following simulation condition simflags="-P all" could be specified in the go line starting Victory Process or Device. This means that all processors available will be used. If you want to use a smaller number of processors, you can substitute "all" with a desired number, e.g. simflags="-P 4".
This example demonstrates advanced 3D process and device simulations of a 180-nm Partially Depleted (PD) Silicon-on-Insulator (SOI) MOSFET with body contact , aimed for Radio-Frequency (RF) CMOS applications. It is related to the article
[1] "Optimization of PD-SOI CMOS Process and Devices for RF Applications" (Silvaco Simulation Standard, Vol. 28, No. 1, 2018) .
RF SOI-CMOS is an important technology used in wireless applications such as tuners and power amplifiers, which can involve switching high power levels at high frequencies (GHz). Hence, requirements of lower insertion loss, better isolation, and better linearity have driven the RF CMOS-SOI design.
In this example, the key design parameters for RF-CMOS are computed, which include:
- "on-resistance" (Ron) , mainly related to the channel resistance of a FET;
- "off-capacitance" (Coff) , associated with isolation between ports of a switch. Coff is a combination of a number of linear (interconnects) and nonlinear (gate, gate-to-source/drain, junctions, buried oxide) capacitances;
- breakdown voltage (BV).
Ron*Coff is a key figure-of-merit for RF switch application. MOSFET channel length reduction along with necessary adjustments to doping profile can improve Ron*Coff, while achieving the required BV value.
3D TCAD computation of all the above parameters is demonstrated in this example.
3D Advanced Process Simulation of a PD-SOI MOSFET
First, Victory Process tool is used to build the device structure, by advanced, physics-based simulations. The simulated PD-SOI process and devices are similar to the ones described in the reference [2]:
[2] H. Lee, et al., "Analysis of body bias effect with PD-SOI for analog and RF applications," Solid-State Electronics, vol. 46, 2002, pp. 1169-1176.
The key process features are: the silicon film thickness of 100 nm, buried oxide (BOX) thickness of 100 nm, gate oxide 3.8 nm thick, and 180-nm gate length of the dual poly (n+/p+) gate. The process steps simulated by Victory Process include: shallow trench isolation (STI) etch, boron implant for the threshold voltage (Vth) adjustment, arsenic implant for LDD and source/drain (S/D) of NMOSFET, rapid thermal annealing (1000 deg C). The threshold voltage adjusting ion implant dose is selected to obtain desired Vth.
The PD-SOI MOSFET with body contact outside the channel is simulated with a 3D model, using a layout based on [2]. Due to symmetry, only half of the entire MOSFET device can be modeled, which saves the simulation time.
3D Numerical Mesh
Next, the Silvaco new Victory Mesh tool is used for appropriate 3D meshing of the structure. Based on the shapes of materials (boundaries) and doping profiles, a locally-refined 3D mesh is generated to appropriately resolve all the 3D geometrical features and the electrical intricacies of the device. The remeshing procedure in Victory Mesh is highly automated.
3D Device Simulations
Then, a number of different device characteristics are simulated using Victory Device simulator, which include:
- Specification of materials, models, and simulation parameters
- Simulation of steady-state Id-Vg characteristics (which allow to determine Vth and DIBL), Id-Vd characteristics (which allow to determine Ron), and breakdown voltage (BV) characteristics
- Computation of small-signal (AC) capacitance-voltage (C-V) characteristics, which allow to determine Coff
- Display of the results in TonyPlot
First, the initial solution is obtained (for zero bias). Then, the Id-Vg transfer characteristics are computed, for selected Vds voltages, from which the threshold voltage (Vth) can be extracted.
Next, the Breakdown I-V characteristic of the 180nm PD-SOI body-tied MOSFET is computed, for the gate bias Vg = 0 V.
Small-signal (AC) Capacitance-Voltage (C-V) Characteristics
As next step, small-signal (AC) 3D TCAD simulations are performed using Victory Device, to obtain C-V characteristics of all the intrinsic capacitances of the MOSFET device. In this example, we demonstrate computation of the Capacitances vs. Gate Voltage (C-Vg) characteristics, which allows to determine the components of Coff (see [1]).
The I-V and C-V curves are plotted using the Silvaco TonyPlot tool.
To load and run this example, select the Load button in DeckBuild > Examples. This will copy the input file and any support files to your current working directory. Select the Run button in DeckBuild to execute the example.
Input Deck
# (c) Silvaco Inc., 2019
# soiex13.in : 3D PD-SOI MOSFET Analysis for RF CMOS Applications
# NOTE:
# By default Victory Process and Victory Device run on just one processor.
# To ensure better performance on your computer, you can specify
# simflags="-P all"
# in the 'go' line starting Victory Process or Device.
# This means that all processors available will be used.
# If you want to use a smaller number of processors, you can
# substitute "all" with a desired number, e.g.
# simflags="-P 4"
go victoryprocess simflags="-P 1"
# Upper boundary of the layout area used:
set Ymax=0.63
init material=silicon mask=soiex13.lay depth=2 gasheight=1 \
dopants=boron dopingvalues=1e15 from="0, 0" to="1.26, $Ymax"
line x location=0 spacing=0.09
line x location=0.09 spacing=0.09
line x location=0.27 spacing=0.09
line x location=0.54 spacing=0.01
line x location=0.63 spacing=0.02
line x location=0.72 spacing=0.01
line x location=0.99 spacing=0.09
line x location=1.17 spacing=0.09
line x location=1.26 spacing=0.09
line y location=0 spacing=0.09
line y location=0.18 spacing=0.09
line y location=0.27 spacing=0.09
line y location=0.36 spacing=0.09
line y location=0.54 spacing=0.09
line y location=0.72 spacing=0.09
line y location=0.9 spacing=0.09
line y location=1.08 spacing=0.09
line y location=1.26 spacing=0.09
line z location=-0.4038 spacing=0.01
line z location=-0.3838 spacing=0.01
line z location=-0.2938 spacing=0.02
line z location=-0.2038 spacing=0.00095
line z location=-0.2 spacing=0.00095
line z location=-0.15 spacing=0.02
line z location=-0.1 spacing=0.01
line z location=-0.05 spacing=0.02
line z location=0 spacing=0.01
line z location=0.2 spacing=0.05
line z location=2 spacing=0.5
# Create Buried Oxide
deposit material=oxide thickness=0.1 max
# Create Active Silicon Film
deposit material=silicon thickness=0.1 max
# Trench Etch
etch material=silicon thickness=0.15 max mask=ACTIVE
etch material=oxide thickness=0.15 max mask=ACTIVE
etch material=silicon thickness=0.2 dry mask=ACTIVE angle=86 deltacd=0.0002
# Grow Oxide and Trench Fill - No point in doing real oxidation
deposit material=oxide thickness=0.0038 max
#export structure=deposited_oxide.str
# Vt Adjust Implant
set vt_dose=2.6e12
set vt_ions=1e5
implant boron energy=15 dose=$vt_dose tilt=7 rotation=27 bca n.ion=$vt_ions
implant boron energy=15 dose=$vt_dose tilt=7 rotation=117 bca n.ion=$vt_ions
implant boron energy=15 dose=$vt_dose tilt=7 rotation=207 bca n.ion=$vt_ions
implant boron energy=15 dose=$vt_dose tilt=7 rotation=297 bca n.ion=$vt_ions
diffuse time=2 temperature=1000
# Poly Gate
deposit material=polysilicon thickness=0.09 max
etch material=polysilicon thickness=0.1 max mask=GATE
export 2D structure=2Dcut.str y=$Ymax
extract init infile="2Dcut.str"
extract name="Vt-adjust implant dose (x4) [1/cm2] " $vt_dose
extract name="Vt implant n.ions " $vt_ions
# LDD Implant
implant arsenic energy=10 dose=2.6e12 tilt=7 rotation=27 bca n.ion=1e5
implant arsenic energy=10 dose=2.6e12 tilt=7 rotation=117 bca n.ion=1e5
implant arsenic energy=10 dose=2.6e12 tilt=7 rotation=207 bca n.ion=1e5
implant arsenic energy=10 dose=2.6e12 tilt=7 rotation=297 bca n.ion=1e5
diffuse time=2 temperature=1000
# Spacer around Poly Gate
deposit material=nitride thick=0.09 conformal curved
etch material=nitride thickness=0.1 max mask=GATE deltacd=0.09
etch material=nitride thickness=0.1 max mask=GATE reverse
deposit material=polysilicon thickness=0 max
etch material=polysilicon mask=GATE thick=0.3 max
# SD Implant
implant arsenic energy=20 dose=1e15 tilt=0 rotation=0 bca n.ion=4e5
diffuse time=2 temperature=1000
# Etch Polysilicon
etch material=polysilicon thickness=0.3 max mask=P_PLUS
etch material=nitride thickness=0.3 max mask=P_PLUS
# P well Contact Implant
mask mask=P_PLUS deltacd=0.09
implant boron energy=5 dose=1e14 tilt=0 rotation=0 bca n.ion=4000000
strip material=barrier
diffuse time=0.417 temperature=1000
# Contact Etch
mask mask=CONT reverse
etch material=oxide thickness=0.0538 min
deposit material=aluminum thickness=0.2038 min
strip material=barrier
Electrodes mask=CONT material=aluminum
# Save files for Victory Mesh remeshing
save name=soiex13_VProc
###################################################################
go victorymesh simflags="-P 1"
load in=soiex13_VProc
remesh conformal
save out=soiex13_VMesh
tonyplot3d soiex13_VMesh.str -set soiex13_mesh.set
tonyplot3d soiex13_VMesh.str -set soiex13_net.set
###################################################################
go victorydevice simflags="-P 1"
# Current Scaling to account for the actual Gate Width (192um)
set CurrScal = 192/0.27
mesh infile=soiex13_VMesh.str
electrode name=substrate z.min=1.9 z.max=2.1
material material=polysilicon taun0=1e-9 taup0=1e-9
models fermi
models material=polysilicon srh
models material=silicon consrh shi fldmob
method pas norm.scaling.local dvmax=0.05 climit=1e-4 linear.max.iterations=1000
solve init
solve previous
save outfile=soiex13_3D_0V.str
####################### Id-Vg Characteristics ##################
# Unsaturated Id-Vg: at Vd=50mV
solve vdrain=0.0001
solve vdrain=0.001
solve vdrain=0.01
solve vdrain=0.05
log outfile=soiex13_Vd50mV.log
solve vgate=0.001
solve vgate=0.01
solve vgate=0.05 vstep=0.05 vfinal=2 name=gate
extract name="Vt_@_Vd=50mV " \
(xintercept(maxslope(curve(abs(v."gate"),abs(i."drain")))) \
- abs(ave(v."drain"))/2)
extract name="Id_lin " $CurrScal*max(abs(i."drain"))
extract name="Vt_lin " x.val from curve ((v."gate"), abs(i."drain")) where y.val=1e-7
extract name="Ron_@_Vd50mV [ohm] " 0.05/($CurrScal*max(abs(i."drain")))
log off
#save outfile=Vg2V_Vd50mV.str
# Saturated Id-Vg: at Vd=2.0V
solve init
solve previous
solve vdrain=0.0001
solve vdrain=0.001
solve vdrain=0.01
solve vdrain=0.05 vstep=0.05 vfinal=2 name=drain
log outfile=soiex13_Vd2V.log
solve vgate=0.001
solve vgate=0.01
solve vgate=0.05 vstep=0.05 vfinal=2 name=gate
extract name="Id_sat " $CurrScal*max(abs(i."drain"))
extract name="Vt_sat " x.val from curve ((v."gate"), abs(i."drain")) where y.val=1e-7
extract name="Ron_@_Vd2V [ohm] " 2.0/($CurrScal*max(abs(i."drain")))
log off
#save outfile=Vg2V_Vd2V.str
tonyplot -overlay soiex13_Vd50mV.log soiex13_Vd2V.log
#####################################################################
####
#### Small-signal (AC) Analysis for Capacitance-Voltage (C-V) Char.
####
################ CAPACITANCES to determine C_off ##################
solve init
solve previous
log outfile=soiex13_CV.log
solve vgate=0 vstep=0.2 vfinal=0.4 name=gate AC freq=1e6 aname=drain
extract name="Cds " $CurrScal*y.val from curve(abs(v."gate"),(c."drain""source")) where x.val=0
extract name="Cgs " $CurrScal*y.val from curve(abs(v."gate"),(c."gate""source")) where x.val=0
extract name="Cgd " $CurrScal*y.val from curve(abs(v."gate"),(c."gate""drain")) where x.val=0
extract name="Cgsub " $CurrScal*y.val from curve(abs(v."gate"),(c."gate""substrate")) where x.val=0
extract name="Cdsub " $CurrScal*y.val from curve(abs(v."gate"),(c."drain""substrate")) where x.val=0
log off
tonyplot soiex13_CV.log -set soiex13_CVg.set
####################### BREAKDOWN Id-Vd #####################
go victorydevice simflags="-80 -P 1"
# Current Scaling to account for the actual Gate Width (192um)
set CurrScal = 192/0.27
Load infile=soiex13_3D_0V.str master
material material=polysilicon taun0=1e-9 taup0=1e-9
models fermi
models material=polysilicon srh
models material=silicon consrh shi fldmob
impact selb
method pas norm.scaling.local dvmax=0.05 climit=1e-4 linear.max.iterations=1000
#solve init
solve previous
solve vdrain=0.0001
solve vdrain=0.001
solve vdrain=0.01
log outfile=soiex13_BV.log
solve vdrain=0.1
solve vdrain=0.25
solve name=drain vstep=0.25 vfinal=100 compl=1e-5 cname=drain
save outfile=soiex13_3D_BV.str
tonyplot soiex13_BV.log -set soiex13_BV.set
extract name="BV [V] " max(abs(v."drain"))
log off
quit
