• TCAD Examples

soiex13.in : 3D PD-SOI MOSFET Analysis for RF CMOS Applications

Requires: Victory Process - Victory Device
Minimum Versions: Victory Process 7.30.4.R, Victory Mesh 1.4.6.R, Victory Device 1.14.1.R

By default Victory Process and Device run on just one processor. To ensure better performance on your computer, the following simulation condition simflags="-P all" could be specified in the go line starting Victory Process or Device. This means that all processors available will be used. If you want to use a smaller number of processors, you can substitute "all" with a desired number, e.g. simflags="-P 4".

This example demonstrates advanced 3D process and device simulations of a 180-nm Partially Depleted (PD) Silicon-on-Insulator (SOI) MOSFET with body contact , aimed for Radio-Frequency (RF) CMOS applications. It is related to the article

[1] "Optimization of PD-SOI CMOS Process and Devices for RF Applications" (Silvaco Simulation Standard, Vol. 28, No. 1, 2018) .

RF SOI-CMOS is an important technology used in wireless applications such as tuners and power amplifiers, which can involve switching high power levels at high frequencies (GHz). Hence, requirements of lower insertion loss, better isolation, and better linearity have driven the RF CMOS-SOI design.

In this example, the key design parameters for RF-CMOS are computed, which include:

  • "on-resistance" (Ron) , mainly related to the channel resistance of a FET;
  • "off-capacitance" (Coff) , associated with isolation between ports of a switch. Coff is a combination of a number of linear (interconnects) and nonlinear (gate, gate-to-source/drain, junctions, buried oxide) capacitances;
  • breakdown voltage (BV).

Ron*Coff is a key figure-of-merit for RF switch application. MOSFET channel length reduction along with necessary adjustments to doping profile can improve Ron*Coff, while achieving the required BV value.

3D TCAD computation of all the above parameters is demonstrated in this example.

3D Advanced Process Simulation of a PD-SOI MOSFET

First, Victory Process tool is used to build the device structure, by advanced, physics-based simulations. The simulated PD-SOI process and devices are similar to the ones described in the reference [2]:

[2] H. Lee, et al., "Analysis of body bias effect with PD-SOI for analog and RF applications," Solid-State Electronics, vol. 46, 2002, pp. 1169-1176.

The key process features are: the silicon film thickness of 100 nm, buried oxide (BOX) thickness of 100 nm, gate oxide 3.8 nm thick, and 180-nm gate length of the dual poly (n+/p+) gate. The process steps simulated by Victory Process include: shallow trench isolation (STI) etch, boron implant for the threshold voltage (Vth) adjustment, arsenic implant for LDD and source/drain (S/D) of NMOSFET, rapid thermal annealing (1000 deg C). The threshold voltage adjusting ion implant dose is selected to obtain desired Vth.

The PD-SOI MOSFET with body contact outside the channel is simulated with a 3D model, using a layout based on [2]. Due to symmetry, only half of the entire MOSFET device can be modeled, which saves the simulation time.

3D Numerical Mesh

Next, the Silvaco new Victory Mesh tool is used for appropriate 3D meshing of the structure. Based on the shapes of materials (boundaries) and doping profiles, a locally-refined 3D mesh is generated to appropriately resolve all the 3D geometrical features and the electrical intricacies of the device. The remeshing procedure in Victory Mesh is highly automated.

3D Device Simulations

Then, a number of different device characteristics are simulated using Victory Device simulator, which include:

  • Specification of materials, models, and simulation parameters
  • Simulation of steady-state Id-Vg characteristics (which allow to determine Vth and DIBL), Id-Vd characteristics (which allow to determine Ron), and breakdown voltage (BV) characteristics
  • Computation of small-signal (AC) capacitance-voltage (C-V) characteristics, which allow to determine Coff
  • Display of the results in TonyPlot

First, the initial solution is obtained (for zero bias). Then, the Id-Vg transfer characteristics are computed, for selected Vds voltages, from which the threshold voltage (Vth) can be extracted.

Next, the Breakdown I-V characteristic of the 180nm PD-SOI body-tied MOSFET is computed, for the gate bias Vg = 0 V.

Small-signal (AC) Capacitance-Voltage (C-V) Characteristics

As next step, small-signal (AC) 3D TCAD simulations are performed using Victory Device, to obtain C-V characteristics of all the intrinsic capacitances of the MOSFET device. In this example, we demonstrate computation of the Capacitances vs. Gate Voltage (C-Vg) characteristics, which allows to determine the components of Coff (see [1]).

The I-V and C-V curves are plotted using the Silvaco TonyPlot tool.

To load and run this example, select the Load button in DeckBuild > Examples. This will copy the input file and any support files to your current working directory. Select the Run button in DeckBuild to execute the example.

Input Files
Output Results
These examples are for reference only. Every software package contains a full set of examples suitable for that version and are installed with the software. If you see examples here that are not in your installation you should consider updating to a later version of the software.
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