Silicon NanoWire Gate-All-Around Tunneling Field-Effect Transistor (TFET) : Silicon NanoWire Gate-All-Around Tunneling Field-Effect Transistor (TFET)

Requires: Atlas
Minimum Versions: Atlas 5.28.1.R

This example demonstrates the capability of a TCAD simulation for Silicon NanoWire (NW) Gate-All-Around (GAA) Tunneling Field-Effect Transistor (TFET) using the non-local band-to-band tunneling (BTBT) model.

This example is related to the IEEE T-ED publication: Z. Y. Chen et al., "Demonstration of Tunneling FETs Based on Highly Scalable Vertical Silicon Nanowires," in IEEE Electron Device Letters, vol. 30, no. 7, pp. 754-756, July 2009, and to the Silvaco Simulation Standard 2017 article "TCAD Simulations of TFET and Tunneling Diode".

This gives an example of using the BBT.NONLOCAL , QTX.MESH , and QTY.MESH models to study the Id-Vg characteristics of a Si NW-GAA-TFET at room temperature (300K) with two different drain voltages, 1.2 V and 0.05 V.

The deck uses the LOOP statement to loop commands in DeckBuild.

The LOOP is used to modify the drain voltage for two Id-Vg simulations. The TFET has a fine mesh at the junctions, specifically at the tunneling junction between the p and i regions. For tunneling to occur in the simulation, the p-i junction is overlayed with a quantum mesh. This quantum mesh is defined by the statement: QTX.MESH and QTY.MESH . This creates simple mesh for planar tunneling junctions.

The model BBT.NONLOCAL is specified on the MODELS statement to use the non-local tunneling model. The direction of tunneling is specified by the QTUNN.DIR statement, with 0 being the y-direction and 1 being the x-direction.

The structure file of each device in equilibrium is saved, and can be viewed in Tonyplot . You can view the band diagrams and other information about the device.

To load and run this example, select the Load button in DeckBuild > Examples. This will copy the input file and any support files to your current working directory. Select the Run button in DeckBuild to execute the example.