powerex23.in : 3D Process and Device Simulation of a Split-Gate Trench UMOSFET
Requires: Victory Process - Victory Device
Minimum Versions: Victory Process 7.76.1.R, Victory Mesh 1.9.0.R, Victory Device 1.20.0.R
By default Victory Process and Victory Device run on just one processor. To ensure better performance on your computer, the following simulation condition simflags="-P all" could be specified in the go line starting Victory Process or Device. This means that all processors available will be used. If you want to use a smaller number of processors you can substitute "all" with a desired number, e.g. simflags="-P 4".
This example demonstrates advanced 3D process and device simulations for a U-shaped trench power MOSFET called Split-Gate Trench UMOSFET . It is related to the Silvaco Simulation Standard (Vol.28, No.1, 2018) article "Advanced Process and Device 3D TCAD Simulation of Split-Gate Trench UMOSFET".
For the low to medium voltage ranges (12 V ~ 250 V), the split gate structures have become prevalent in the power MOSFET technologies. They allow to achieve the best trade-off between the breakdown voltage (BV) and specific on-state resistance (Rsp) for the vertical discrete power MOSFETs. Most of these solutions are based on the RESURF (Reduced Surface Field) action of Split-Gate Resurf Stepped Oxide (SG-RSO) along the drift region.
In the split-gate (SG) version of UMOSFET the bottom part of the gate, called Field Plate or Split Gate, is isolated from the gate so that the upper part next to the channel (the actual gate) and the lower part next to the drift region (the field plate) are connected independently, the field plate being usually connected to the source (grounded). This results in a drastic decrease in the capacitance between the gate and the drain (Cgd) while still maintaining the RESURF effect induced by the field plate.
3D Advanced Process Simulation of a Split-Gate UMOSFET
In the first part of this example, Victory Process tool is used to build the device structure, by advanced, physics-based simulations of several process steps commonly used for modern Split-Gate UMOS fabrication. The simulated process steps include: a) formation of a deep trench with rounded bottom, by a combination of Dry and Wet Etch steps, b) shield (thick) oxide growth, c) shield poly (field plate) deposition, d) inter-poly oxide deposition and etch back to obtain the thinner gate-oxide, e) gate poly deposition and etch back, f) core contact etching and deposition of the contact plug and metallization (for the Source contact).
3D Numerical Mesh
Next, the Silvaco new Victory Mesh tool is used for appropriate 3D meshing of the structure. Based on the complex shapes of materials (boundaries) and doping profiles, a 3D Delaunay mesh is generated to appropriately resolve all the complex 3D geometrical features and the electrical intricacies of the device.
3D Device Simulations
Then, a number of different device characteristics are simulated using Victory Device simulator, which include:
- Specification of materials, models, and simulation parameters
- Simulation of steady-state Id-Vg, gm-Vg, Id-Vd, and breakdown voltage (BV) characteristics
- Computation of small-signal (AC) capacitance-voltage (C-V) characteristics
- Display of the results in TonyPlot
First, the initial solution is obtained (for zero bias). Then, the Id-Vg transfer characteristics are computed, from which the threshold voltage (Vth) and the transconductance gm-Vg characteristics can be extracted.
Next, the Id-Vd output characteristics are computed, for a selected Vgs bias voltage.
Then, the Breakdown I-V characteristic of the Split-Gate UMOSFET is computed, for the gate bias Vg = 0 V.
The I-V curves are plotted using the Silvaco TonyPlot tool. The transconductance gm (dId/dVg) curve can be plotted using Display > Functions... feature in TonyPlot.
Small-signal (AC) Capacitance-Voltage (C-V) Characteristics
As next step, small-signal (AC) 3D TCAD simulations are performed using Victory Device, to obtain C-V characteristics of all the intrinsic capacitances of the UMOS device. In this example, we demonstrate computation of the Capacitances vs. Drain Voltage (C-Vd) characteristics, which are often important for power MOSFETs.
To load and run this example, select the Load button in DeckBuild > Examples. This will copy the input file and any support files to your current working directory. Select the Run button in DeckBuild to execute the example.
Input Deck
# (c) Silvaco Inc., 2022 # powerex23.in : 3D Process and Device Simulation of a Split-Gate Trench UMOSFET # NOTE: # By default Victory Process and Victory Device run on just one processor. # To ensure better performance on your computer, you can specify # simflags="-P all" # in the 'go' line starting Victory Process or Device. # This means that all processors available will be used. # If you want to use a smaller number of processors, you can # substitute "all" with a desired number, e.g. # simflags="-P 8" go victoryprocess # simflags="-P 8" # Set geometrical parameters of the device # Substrate depth set SubstrThic=2 # Substrate doping set SubstrDopd=3e19 # Half of the pitch set HPitch=0.44 #Thickness of Epi layer set EpiThic=3.0 # Phosphorus concentration in epi layer set EpiDop=2e16 # Trench slope angle set Angle=87 # Half of trench width set HTrenchWidth=0.25 # Trench depth set TrenchDepth=1.8 # Radius at the bottom of the trench as portion of HTrenchWidth # This parameter should be 0 < RAD < 0.9 set RadFrac=0.5 # Radius at the bottom of the trench in microns set Radius=$RadFrac*$HTrenchWidth # Thickness of nitride mask used for geometrical etch of "sloped" and "rounded" trench set MaskThic=0.3 # # Polysilicon Split-Gate (shield poly) height/thickness set SGatePolyThic=0.7 # Oxide thickness between Poly gates set ipOxThick=0.15 # Polysilicon Gate deposition height/thickness set GatePolyThic=0.44 # Gate oxide thickness set GateOxThick=0.03 # set Pi=3.141593 # # Basic RESOLUTION for etch/depo and oxidation simulation set Resolut=0.03 # Uncomment this to build geometry only, without doping #option run.geometry init meshdepth=2 orientation=100 from="0.0,0.0" to="$HPitch,$HPitch" depth=$SubstrThic gasheight=10 resolution=$Resolut material=silicon dopants="phosphorus" dopingvalues=$SubstrDopd surface.z=$EpiThic # ------ Base volume 3D grid ---------------- Line x location=0.0 spacing=0.2 Line x location=$HPitch spacing=0.2 Line y location=0.0 spacing=0.2 Line y location=$HPitch spacing=0.2 # Line z location=-2 spacing=0.5 Line z location=0.5*$EpiThic spacing=1 Line z location=$EpiThic spacing=0.2 Line z location=$SubstrThic+$EpiThic spacing=1 # ------------------------------------------------ #method dif.SolverMultiThreading=on method flow.SolverMultiThreading=off flow.Solver="bicgstab" flow.Preconditioner="ilk" Epitaxy time=15 temperature=1100 thickness=$EpiThic dopants="phosphorus" dopingvalues=$EpiDop # Form a trench with rounded bottom, by combination of DRY and WET etch steps Deposit material=nitride thickness=$MaskThic conformal set RAD0=$HTrenchWidth-$Radius+$MaskThic/tan($Pi*$Angle/180.0) Specifymaskpoly mask="circle0" circle npoints=36 center="0.0,0.0" radius=$RAD0 Etch thick=$TrenchDepth-$Radius+$MaskThic dry angle=$Angle mask="circle0" reverse ref.z=-$MaskThic Specifymaskpoly mask="circle1" circle npoints=36 center="0.0,0.0" radius=$HTrenchWidth Etch wet thickness=$Radius mask="circle1" reverse Strip material=nitride #Trench oxidation and oxide CVD Diffuse time=6 temperature=1050 dryo2 press=1.00 hcl=3 deposit material=oxide thickness=0.1 conformal # Extract oxide thickness on the trench bottom and sidewall Export 2D structure=2dx.str y=0 extract init infile="2dx.str" extract name="bottomox" thickness material="SiO~2" mat.occno=1 x.val=0.005 extract name="sideox" thickness material="SiO~2" mat.occno=1 y.val=0.7 # Split-gate poly deposition deposit material=polysilicon thick=$SGatePolyThic thicknessStep=5 min dopants="phosphorus" dopingvalues="1e20" # "etchback" the thick oxide to achieve required ipOxThick and GateOxThick set wetetchthickness=(1e-4*$sideox)-$GateOxThick deposit material=oxide thickness=$ipOxThick+$wetetchthickness min etch material=oxide thick=$wetetchthickness thicknessStep=5 wet # Deposit Polysilicon Gate Deposit material=polysilicon thick=$GatePolyThic thicknessStep=5 dopants="phosphorus" dopingvalues="1e20" min # Extract the gate position and oxide thickness Export 2D structure=2dx1.str y=0 extract init infile="2dx1.str" extract name="gatetop" min.bound polysilicon mat.occno=1 x.val=0.05 extract name="gatebottom" max.bound polysilicon mat.occno=1 x.val=0.05 extract name="GateOx_farXpos" max.bound oxide mat.occno=1 y.val=0.5*($gatetop +$gatebottom) extract name="TrenchBottom" max.bound oxide mat.occno=2 x.val=0.005 # minimum spacing in X direction set XSP=0.012 Line x loc=$GateOx_farXpos-2*$XSP spacing=$XSP Line x location=$GateOx_farXpos+2*$XSP spacing=$XSP Line y loc=$GateOx_farXpos-2*$XSP spacing=$XSP Line y location=$GateOx_farXpos+2*$XSP spacing=$XSP # Minimum spacing in Z direction set ZSP=0.03 Line remove z location=0.5*$EpiThic spacing=1 line z location=$gatetop spacing=$ZSP line z location=$gatebottom spacing=$ZSP # Pwell doping Implant boron energy=200 dose=2.3e12 set BDIFFTIME=50 Diffuse time=$BDIFFTIME temperature=1050 # Add fine grid to capture N+ implant Line z location=0.1 spacing=0.01 etch material=oxide thickness=0.06 max # N+ implant and drive set NPLUSDOSE=2e15 Implant arsenic dose=$NPLUSDOSE energy=10 tilt=7 Diffuse time=30 temperature=950 # Isolation oxide and recessed etch for P+ implant and Source contact Deposit material=oxide thick=0.5 conformal thicknessStep=5 Specifymaskpoly mask="circle2" circle npoints=36 center="0.0,0.0" radius=($HPitch-0.08) Etch material=oxide mask="circle2" dry thickness=1 Etch material=silicon thick=0.5 dry # P+ implant and drive set PPLUSDOSE=6e12 Implant boron dose=$PPLUSDOSE energy=15 tilt=0 Diffuse time=2 temperature=800 # Contact metal deposition #Deposit material=tungsten thick=0.1 conformal Deposit material=aluminum thick=0.2 conformal # Assign electrods Electrode name=gate x=0.05 y=0.05 z=0.5*($gatetop +$gatebottom) Electrode name=sgate x=0.025 y=0.025 z=$Trenchbottom-0.5 Electrode name=source x=0.05 y=0.05 Electrode name=drain substrate Export 2D structure=2Dcut_VPfinal.str y=0 extract init infile="2Dcut_VPfinal.str" extract name="side_gateox" thickness material="SiO~2" mat.occno=1 y.val=0.6 # Save files for Victory Mesh remeshing Save name=powerex23_VP ############################################################################# ############################################################################# go victorymesh # simflags="-P 8" load in=powerex23_VP set MaxSIZE=0.07 set MaxMOSSIZE=0.005 set MaxJuncSIZE=0.01 set MaxIntSIZE=0.02 remesh delaunay refine max.size=$MaxSIZE regions="*" refine max.size=0.4*$MaxSIZE regions="material:polysilicon" refine max.interface.size=$MaxMOSSIZE grading="quadratic" refine max.junction.size=$MaxJuncSIZE grading="quadratic" refine regions="sio2" max.interface.size=$MaxIntSIZE grading="quadratic" \ interface.regions="sio2" other.interface.regions="polysilicon,silicon" save out=powerex23_delaunay.str tonyplot3d powerex23_delaunay.str -set powerex23_structure.set ############################################################################## ############################################################################## ############################################################################## go victorydevice # simflags="-P 8" ############# Computation of Id-Vg Characteristics ############### ############# and Threshold Voltage (Vth) ############### mesh infile="powerex23_delaunay.str" # Select physics models models material=silicon cvt srh print contact name=gate n.poly interface qf=3e10 #method pas method pam.bicgst solve init #save outfile=powerex23_0V.str # Bias the drain solve vdrain=0.1 log outfile=powerex23_idvg.log # Ramp the gate voltage solve vgate=0 vstep=0.2 vfinal=6.0 name=gate # extract Vth extract name="Vth" (xintercept(maxslope(curve(abs(v."gate"),abs(i."drain")))) \ - abs(ave(v."drain"))/2.0) log off tonyplot powerex23_idvg.log -set powerex23_idvg.set ############################################################################## go victorydevice # simflags="-P 8" ############# ID-VD Computation: Returns Id-Vd curve ######## mesh infile="powerex23_delaunay.str" # Select physics models models material=silicon cvt srh print contact name=gate n.poly interface qf=3e10 #method pas method pam.bicgst solve init # Bias the gate solve vgate=0 vstep=0.25 vfinal=5.0 name=gate # Ramp the drain bias voltage set vdmax=50 log outfile=powerex23_idvd.log solve vdrain=0.05 solve vdrain=0.2 solve vdrain=0.5 solve name=drain vstep=0.5 vfinal=8 solve name=drain vstep=1.0 vfinal=20 solve name=drain vstep=2.0 vfinal=$vdmax # Current scaling: quarter device (4x) * number of cells set currScale=4 extract name="Rds_ON " $vdmax/($currScale*max(abs(i."drain"))) log off tonyplot powerex23_idvd.log -set powerex23_idvd.set ############################################################################## go victorydevice simflags="-80" # simflags="-80 -P 8" ##### Computation of Drain-Source Breakdown Voltage (BVDSS) ####### mesh infile="powerex23_delaunay.str" models material=silicon cvt srh print impact selb contact name=gate n.poly interface qf=3e10 #method pas method pam.bicgst climit=1e-4 solve init # log outfile=powerex23_BV.log solve vdrain=0.1 solve vdrain=0.5 solve name=drain vstep=0.5 vfinal=2 solve name=drain vstep=1.0 vfinal=10 solve name=drain vstep=2.0 vfinal=40 solve name=drain vstep=1.0 vfinal=70 cname=drain compliance=5e-7 extract name="BVDSS" max(v."drain") log off tonyplot powerex23_BV.log -set powerex23_bv.set #save outfile=powerex23_BV.str ############################################################################## go victorydevice simflags="-80" # simflags="-80 -P 8" ####### Compute Capacitances vs. Drain Voltage (C-Vd) ############ mesh infile="powerex23_delaunay.str" models material=silicon cvt srh print contact name=gate n.poly interface qf=3e10 #method pas method pam.gmres solve init solve vgate=0 log outfile=powerex23_CVd.log # Ramp the drain voltage and do small-signal AC analysis for each Vd solve vdrain=0 vstep=0.25 vfinal=2.0 name=drain AC freq=1e6 solve vdrain=3 vstep=1.0 vfinal=10 name=drain AC freq=1e6 tonyplot powerex23_CVd.log -set powerex23_cvd.set quit
