powerex02.in : Vertical DMOS Turn-on Characteristics

Requires: SSuprem 4/S-Pisces/Giga
Minimum Versions: Athena 5.22.3.R, Atlas 5.34.0.R

This example demonstrates fabrication and electrical analysis of a vertical DMOS structure. It shows:

• DMOS process flow to generate the device structure using Athena
  
• Model setup for non-isothermal device simulation using Giga
  
• Atlas methodology for simulating the DMOS device gate characteristics

The structure generated by Athena is a silicon vertical DMOS device. A phosphorus doped silicon substrate and underlying mesh are defined. A lightly phosphorous doped silicon epitaxial layer is then grown using the epitaxy command. The gate material is deposited, patterned and etched. Boron is implanted and diffused to form the right edge of channel region under the gate. The source region arsenic implant is performed and diffused to complete the channel definition. Aluminum is deposited and etched to form the source contact. The source, drain and gate electrodes are defined by using the electrode statement and by including the name and location of the contact on the command line. Notice that the drain electrode location is defined by the 'electrode' command line option backside . Now that the structure has been completed, the Atlas device test can be performed.

In this simulation, the structure created by Athena will be automatically loaded into Atlas when the command go atlas is reached. The contact statement sets the workfunction for the gate to that of degenerately doped n-type polysilicon. Next, the models statement sets the physical transport and associated models to be used, in this case, conmob: concentration dependent mobility, fldmob: lateral electric field dependent mobility, srh: Shockly-Read-Hall recombination, and most importantly for power devices, lat.temp: non-isothermal transport using Giga. The thermal boundary condition for the source contact is defined by the thermcontact statement.

The gate characteristics of this DMOS device are calculated by solving the transport and thermal equations at the bias specified in the solve statements. Here, the drain bias is stepped to 20 volts. Next, an output logfile is opened using the log command, and the gate contact is ramped from 0.25 volts to 20 volts in two stages. It is advisable to use smaller bias steps initially. Larger bias steps can then be used for the remaining bias range. TonyPlot plots the gate characteristics from the log file. To plot the structure and solution at the final bias point, highlight the name 'powerex02_2.str' on the save command line and click left 'Tools' at the top right of the DeckBuild window.

To load and run this example, select the Load button in DeckBuild > Examples. This will copy the input file and any support files to your current working directory. Select the Run button in DeckBuild to execute the example.