• TCAD Examples

    TCAD Examples

mos2ex06.in : BSIM3 SPICE Model Extraction (Salicide process)

Requires: SSuprem 4/S-Pisces/Utmost
Minimum Versions: Athena 5.22.3.R, Atlas 5.32.0.R

This example demonstrates the extraction of a BSIM3 SPICE model from Atlas simulation data of an NMOS transistor. The example:

  • Forms a MOS device in Athena using a salicide process
  • Uses assigned variables to parameterize the structure
  • Simulates Id/Vgs-Vbs curves in Atlas
  • Simulates Id/Vds-Vgs curves in Atlas
  • Interfaces to UTMOST for extraction of a BSIM3 parameter set.

The process simulation used for this example is an NMOS process flow. Further description of MOS process simulation can be found in the MOS examples description. As a more advanced technique, this flow has been parameterized in places using the set statements. These are used to assign variables such as spacer width which are then used later in several locations in the input file. extract statements are used throughout the process simulation to measure important process parameters. In terms of the SPICE model extraction, it is vital to extract the gate oxide thickness in metres for use in UTMOST.

The salicide process to create self-aligned silicides on the source, drain and gate requires the use of the Athena/SILICIDES module. Users who do not have this option could replace the silicidation steps with metal deposition and patterning as used in the previous MOS examples. In this transistor, titanium silicide is used. A titanium layer is deposited and a short heat cycle applied. No special method parameters are needed to enable creation of the silicide layer during this diffusion. The remaining titanium is then stripped. These silicide regions are indicated in the electrode definition in Athena.

The two Atlas runs in this example are also parameterized using the set statement. This enables easy conversion of the whole Id/Vgs and Id/Vds tests from, say, NMOS to PMOS or 5.0V supply to 3.3V.

The first Atlas run simulates Id/Vgs curves at three substrate biases. The sequence of solve statements is to first save three solutions at each back bias with Vds=0.1V and Vgs=0.0V. Each of these three files is then loaded in turn using load and the gate voltage ramped up to the supply voltage defined as 'vdsmax'. In this example all three curves are saved to a single log file. However it is more traditional to save the three curves in separate files. Either approach is possible.

The second Atlas run simulates Id/Vds curves at three different gate voltages. A similar technique to the first run is used. Three solution files are saved at each gate bias with Vds=0.0V. These are then loaded in turn and the drain voltage ramped to 'vdsmax'. All the curves are saved to a single log file although separate ones could be used for each curve.

The final stage of the example is to run UTMOST to extract the SPICE model. Important information about the structure such as gate oxide thickness and gate length is transferred to UTMOST using the results of extract statements in the Athena simulation. The log files from Atlas are loaded and appended together. UTMOST then fits the SPICE model to the complete Id/Vgs-Vbs and Id/Vds-Vgs data sets. All the UTMOST parameters are stored to a file and then extract is used to print out the parameters of interest.

To load and run this example, select the Load button in DeckBuild > Examples. This will copy the input file and any support files to your current working directory. Select the Run button in DeckBuild to execute the example.

Input Files
Output Results
These examples are for reference only. Every software package contains a full set of examples suitable for that version and are installed with the software. If you see examples here that are not in your installation you should consider updating to a later version of the software.
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