• TCAD Examples

    TCAD Examples

mos1ex11.in : DIBL Extraction

Requires: SSuprem 4/S-Pisces
Minimum Versions: Athena 5.22.3.R, Atlas 5.32.0.R

This is a basic MOS Athena to Atlas interface example simulating two Id/Vgs curves at different drain biases and extracting the drain-induced barrier lowering (DIBL) parameter. This example demonstrates:

  • Process simulation of a MOS transistor in Athena
  • Process parameter extraction (eg. oxide thicknesses)
  • Autointerface between Athena and Atlas
  • Simple Id/Vgs curve generation with Vds=-0.1V
  • Ramp of drain voltage
  • Simple Id/Vgs curve generation with Vds=-3.0V
  • Parameter extraction for the DIBL parameter

The process simulation, process parameter extraction and electrode definition for this example are exactly as described in the first example in this section.

In Atlas, the models, interface and contact statements are also the same as in the first example. The extraction of the first Id/Vgs curve is very similar to the previous threshold voltage extraction example.

One difference is the use of the syntax compl=1.1e-7 cname=drain . This sets a compliance limit on the drain current. Although the SOLVE statement calls for a ramp in gate voltage from zero to -1.5V, once the trigger current specified by compl is exceeded on the electrode specified by cname then the gate voltage ramp will step and Atlas will execute the next line of syntax. Note that the compliance value does not need to be signed. A current more negative than -1.1e-7 will also trigger the compliance limit. Compliances are more commonly used in breakdown simulations but can be used in this way to stop voltage ramps once the area of interest is passed.

All results from the first Id/Vgs curve are saved to the file specified by the first log statement. In Atlas the only way to stop the IV points being saved is either to specify another LOG statement or to use log off or exit the simulator. Here, log off is used to stop the output from the drain voltage ramp being saved to the Id/Vgs logfile specified previously.

The second 'solve init' statement resets all applied voltages to zero. Then the drain is ramped to -3.0V and the gate ramp with compliance is repeated.

After each gate ramp, the threshold voltage was extracted using a different syntax than the PMOS threshold voltage example described earlier in this section. In this example the threshold is determined by looking for the voltage where the drain current reaches a user-defined value. The syntax x.val from curve (x,y) where y.val=<number> is used. At large drain biases this method is preferred for threshold extraction over the steepest slope approach. The search value of 0.1uA/um of current is typical for channel lengths around 1um. These thresholds are stored as values pvt1 and pvt2 in DeckBuild. The final extract statement is used to obtain the DIBL parameter. It is the difference in threshold voltage divided by the difference in the drain bias.

To load and run this example, select the Load button in DeckBuild > Examples. This will copy the input file and any support files to your current working directory. Select the Run button in DeckBuild to execute the example.

Input Files
Output Results
These examples are for reference only. Every software package contains a full set of examples suitable for that version and are installed with the software. If you see examples here that are not in your installation you should consider updating to a later version of the software.
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