• TCAD Examples

imagesensorex04.in : Process and Device simulation

Requires: Athena/Atlas/Luminous
Minimum Versions: Atlas 5.28.1.R

This example demonstrates Process and Device simulation of a CMOS Image sensor (CIS). Front End as well as Back End Process simulation including lens are simulated using Athena. DC as well as Transient IV characteristics under illumination are simulated using Atlas.

The CIS is a special transistor where the source region is the whole floating N- region underneath a heavy P+ doping pin layer. The drain side is a floating diffusion to which the electrons are transfered. The gate is used to transfer electrons from the source to the the drain.

When designing CIS, the depletion region from the image sensor (source contact) should not connect to the depletion region from the drain contact. Therefore, you must isolate the drain contact from the source contact with boron implants.

Also the buried N- region (which is the active sensor) was connected to the channel region under the gate to create a source with further additional implants.

Only by doing this, do you get good connectivity of the image sensor to the drain when the transfer gate is activated.

Vt was adjusted with the boron implant through the poly gate so that no leakage occurs when the light auto-biases the buried N- channel region.

The complete structure was achieved by adding a Back End Process including a lens to focus light in the buried N- layer.

Unsaturated and saturated D.C. IV Characteristics were simulated in order to verify low leakage current all the way up to Vg=1V. For that purpose, artificial source contact in buried N- layer is added to simulate FET IV characteristics.

The Drain is then ramped up to 3.3V and is made floating by setting the current boundary condition.

The light is shone on the structure during 50us. Ray tracing is used in this case but FDTD can also be used and the statements are available in the input deck. For a more detailed description of FDTD syntax please refer to image sensor examples 1 to 3.

From the log file we can see that bias of the buried N- region gradually decreases as the light generated carriers are integrated. At around 3us, the image sensor is saturated, and the voltage can increase no further no matter how much light you shine on it. Note that despite full light shining on the structure, the signal remains de-coupled from the drain (i.e the drain remains at 3.3V before the gate is turned on). This is the result of the back end process shadowing the drain and of the low leakage of the design.

From the structure file rays, photogeneration as well as electron concentration can be seen.

At 50us the gate is ramped in transient to 3.3V to transfer the charge previously generated in the N- region to the floating drain. The potential in the N- region starts to increase in voltage as the electrons from the N- region are transfered to the floating drain region.

To load and run this example, select the Load button in DeckBuild > Examples. This will copy the input file and any support files to your current working directory. Select the Run button in DeckBuild to execute the example.

Additional Info:

Input Files
Output Results
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