Liberty .lib Timing Model Generation

009_core : Liberty .lib Timing Model Generation

Minimum Required Versions: AccuCore 2.4.9.R, SmartSpice 3.16.12.R

This example explains additional detailed not covered in AccuCore Web Example 001_core Chip and Block Characterization Configuration related to how to use AccuCore to create Liberty .lib cell library timing models from a SPICE netlist The SPICE netlist may be either hierarchical or flat and may also contain RC parasitics. This feature is especially useful in legacy IP reverse-engineering applications.

To enable this feature specify synthesis as a MODEL_TYPE in the Core_EX9.cfg file.

Additional .cfg file commands are (additional cmds here)