SURGE Virtual Event Korea 2020
2020년 11월 4일 9:30AM~3:30PM (한국 시각)
실바코 코리아가 2020년 11월 4일에 온라인 SURGE 행사를 개최합니다.
실바코의 SURGE (Silvaco UseRs Global Event)에서 사용자들의 생생한 경험과 혁신적인 기술을 확인할 수 있습니다.
참석자 중 100분께 스타벅스 기프트 카드 만원권을 이메일로 보내드립니다. 실바코의 고객 및 관심 있으신 분들의 많은 참여 바랍니다.
Agenda
| Time | GENERAL SESSION |
|---|---|
| 9:30AM | Welcome and Introduction – Farhad Hayat – Silvaco, Inc. |
| 9:35AM | From Atoms to Systems: Semiconductor Business Trends and Challenges – Babak Taheri – Silvaco, Inc. |
| 10:00AM | Doing Something Wonderful: Fueling the Data Revolution with Advanced Semiconductors – Rahul Goyal – Intel |
| 10:30AM | GLOBALFOUNDRIES’s Specialty Foundry Solutions Accelerating the Digital Future – Richard Trihy – GLOBALFOUNDRIES |
| 11:00AM | Break |
| 11:10AM | TFT Backplane Technologies for Foldable Displays – Jin Jang – Kyung Hee University |
| 11:35AM | Flexible Electronics R&D Platform in ETRI – Jeong-Ik Lee – ETRI (Electronics and Telecommunications Research Insititute) |
| 12:00PM | Virtual Lunch |
| Time | EDA & IP Track |
|---|---|
| 1:00PM | Analog Custom Design Update – Thomas Blaesi – Silvaco, Inc. |
| 1:10PM | Go Faster - SmartSpice Analog Simulation Update – Jody Matos – Silvaco, Inc. |
| 1:30PM | Curing Power, Electro-migration, and IR Drop Problems – Alex Samoylov – Silvaco, Inc. |
| 1:45PM | Jivaro & Viso for Advanced Parasitic Reduction, Analysis and Optimization – Simon-Alexis Abric – Silvaco, Inc. |
| 2:05PM | VarMan, No Compromise High-Sigma Yield Analysis for Standard Cell and Memory – Jean-Baptiste Duluc – Silvaco, Inc. |
| 2:25PM | Design IP Solutions Update – Jeff Elias – Silvaco, Inc. |
| 2:40PM | Reducing the Layout Development Cycle Time for Standard Cells – Sharmistha Sinha, – Sr. Design Engineer, Anand Kumar Mishra Sr. Managers, STMicroelectronics |
| 3:05PM | Optimized Applications for NXP CoolFlux DSP Ultra-low Power Programmable Cores – Johan Van Ginderdeuren – Director, IP Blocks Licensing, NXP Semiconductors |
From Atoms to Systems: Semiconductor Business Trends and Challenges
Babak Taheri
CEO/CTO, Silvaco Inc
Abstract
Babak Taheri, CEO/CTO of Silvaco provides an update on Silvaco products development and a perspective on major trends and challenges facing semiconductor businesses, including dealing with the COVID-19 crisis, what we have learned, and how the new situation affects the market. Different segments including Automotive, IoT, Memory, 5G networks, Security will be covered.
Doing Something Wonderful: Fueling the Data Revolution with Advanced Semiconductors
Rahul Goyal
Vice President and Director of R&D Strategic Enablement, Intel
Abstract
Rahul Goyal will present on the latest industry trends and challenges for creating advanced semiconductors for computing used in a wide range of end markets, including servers, mobile, AI/ML, automotive, and 5G applications. He will address key challenges for Intel in pursuit of heterogeneous integration and Intel’s pillars of technology. He will cover how Intel design community looks to EDA suppliers for TCAD, IP and design analysis and what challenges they see coming in future designs.
GLOBALFOUNDRIES’s Specialty Foundry Solutions Accelerating the Digital Future
Richard Trihy
Vice President of Engineering, Design Enablement, GLOBALFOUNDRIES
Abstract
Mr. Trihy will present trends and challenges for the semiconductor industry from a foundry perspective, and how GLOBALFOUNDRIES’ technology solutions meet the needs of fabless companies to develop innovative products for high-growth market segments. These solutions include GF’s differentiated 22FDX® (22nm FD-SOI) platform and GF’s 12LP finfet and 12LP+ platforms and a full breadth of technologies to support 5G mmWave, edge AI, Internet of Things (IoT), automotive, satellite communications, security, and other applications. He will cover how GF partners with EDA and IP partners like Silvaco for design IP, EDA software, and development of process design kits (PDKs) to meet the dynamic needs of clients across the globe.
GLOBALFOUNDRIES (GF) is the world’s leading specialty foundry. GF delivers differentiated feature-rich solutions that enable its clients to develop innovative products for high-growth market segments. GF provides a broad range of platforms and features with a unique mix of design, development, and fabrication services. With an at-scale manufacturing footprint spanning the U.S., Europe and Asia, GF has the flexibility and agility to meet the dynamic needs of clients across the globe. GF is owned by Mubadala Investment Company.
Frontiers in Memory Technology and Modeling Drivers
Gurtej S. Sandhu
Senior Fellow and Vice President, Micron Technology
Abstract
TBD
From Atoms to Systems: Semiconductor Business Trends and Challenges
Babak Taheri
CEO, Silvaco Inc
Abstract
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TFT Backplane Technologies for Foldable Displays
Jin Jang
Director of the Advanced Display Research Center, Kyung Hee Univeristy
Abstract
Foldable and rollable displays are of increasing interest recently. I will discuss the key technologies of TFTs for those applications. Non-laser detach technology was developed by using a CNTGO buffer layer inserted on carrier glass and then PI substrate coated. A CNT/GO buffer layer helps easy detach and more self-standing of plastic substrate [1]. We made oxide and LTPS TFTs on PI substrate using CNTGO buffer layer and investigated the effect of bending and folding on the electrical properties of TFTs. Tensile stress is found to give more change to the TFT performance for both LTPS and oxide TFTs compared to compressive stress [2]. These results are related with out-folding or in-folding of smartphone displays. The split of both source/drain and semiconductor layer is important for more foldable TFTs [3]. The device performance is also improved a lot by splitting active-layer for oxide TFTs [4]. The TFT in neutral plane is also very robust under bending [5]. I will discuss the strain effect on TFTs with out-folding or in-folding. The effect of grain boundaries on the foldability will be also touched [6-7].
Flexible Electronics R&D Platform in ETRI
Jeong-Ik Lee
Assistant Vice President Reality Devices Research Division, ETRI
Abstract
Flexible electronics has grown as a main stream research field for the potential application to wearable/healthcare monitoring, smart packaging as well as flexible displays. To accelerate technology development and expand the development eco-system of flexible electronics, it is important to establish a R&D platform for flexible electronics. ETRI(Electronics & Telecommunications Research Institute) has worked on flexible displays and accumulated lots of research experience for flexible electronics including conductive metal lines, TFT circuits, and OLEDs on flexible films. By using those experience and the collaboration with SILVACO, we have tried to establish the flexible electronics R&D platform (FERP) and some of efforts have been presented at the last year SURGE. We have checked the status of the FERP by fabricating some flexible electronic devices according to the demand of the external researchers. Based on those results, the progress and current status of the FERP in ETRI will be presented.
Analog Custom Design Update
Thomas Blasei
VP & GM, EDA Division, Silvaco Inc
Abstract
Mr. Blaesi will give the update for the Analog Custom Design Flow and the direction of future development.
Tools and Services Update for SPICE Modeling of Devices
Bogdan Tudor
Senior Manager, Device Characterization, Silvaco Inc
Abstract
Dr. Tudor will present the latest developments in creating SPICE models for simulation uisng Utmost IV software and the Silvaco characterization laboratory.
Go Faster - SmartSpice Analog Simulation Update
Jody Matos
Senior Manager, Simulation, Silvaco Inc
Abstract
Dr. Matos will presesnt how SmartSpice continues to go faster, consume less memory, and provide advanced modeling and analysis of analog ciruits.
Good News - The Silvaco Analog Custom Design Flow
Fred Sendig
Vice President of R&D, Silvaco Inc
Abstract
Mr. Sendig will present the latest developments in the Analog Custom Design flow from schemtic capture, simulation, and analysis to physical layout and verification.
Device and Design Exploration - a New Smarter Approach
Jon Sanders
Director of Product Engineering, Silvaco Inc
Abstract
Mr. Sanders wil present the requirements for a smart model and design exploration aid for analog circuits.
Curing Power, Electro-migration, and IR Drop Problems
Dr. Alex Samoylov
Senior Manager, EM/IR Analysis, Silvaco Inc
Abstract
Mr. Samoylov will present the requirements for a tool that provides extensive analysis capabilities for IR-drop, electromigration, and thermal design issues.
IC Simulation and Verification Solutions: Silvaco Vision and Roadmap
Dr. Firas Mohamed
VP Advanced R&D & GM Silvaco France
Abstract
Dr. Firas Mohamed will give his perspective on the means to achieve practical simulation and Monte Carlo analysis of full-chip analog and memory designs.
Jivaro & Viso for Advanced Parasitic Reduction, Analysis and Optimization
Simon-Alexis Abric
Corporate Application Engineer, Silvaco Inc
Abstract
Mr. Simon-Alexis Abric is a Corporate Application Engineer for Silvaco France. He is responsible for customer technical support for reduction (Jivaro) and parasitic analysis (Alps) products. Mr. Abric earned a Master of Engineering degree in integrated circuits and systems in 2013 from the engineering school ENSEIRB in Bordeaux, France.
VarMan, No Compromise High-Sigma Yield Analysis for Standard Cell and Memory
Jean-Baptiste Duluc
Senior Corporate Application Engineer, Silvaco Inc
Abstract
Dr. Jean Baptiste Duluc is the core-competency application engineer in charge of VarMan product development at Silvaco. He joined Silvaco in 1999 as support engineer for the characterization and modeling software Utmost. Dr. Duluc holds a MS and PhD in microelectronics from the University of Bordeaux, France.
TCAD Simulation Update
Dr. Eric Guichard
VP & GM, TCAD Division, Silvaco Inc
Abstract
Mr. Guichard will give the update for Silvaco TCAD simulation and the direction of future development.
From Ab-Initio Calculations of Material Properties to Quantum Transport Calculations with Victory Atomistic
Carlos Augusto, Ph.D.
Co-Founder and CTO, Quantum Semiconductor
Abstract
With the end of geometric scaling, semiconductor devices are increasingly adopting new materials to increase performance and functionality. Simulating mesoscopic-sized devices with new materials, about which there may be no reliable experimental characterization, requires both a quantum transport simulator such as Victory Atomistic, and Density Functional Theory (DFT) calculations of the fundamental optoelectronic properties of the new materials. The linking of DFT codes with Victory Atomistic is crucial for a complete TCAD workflow to explore leading edge CMOS, Lasers, Heterojunction Photo-Diodes, and more. Quantum Semiconductor LLC is working with Silvaco on the simulation of photo-absorption in direct band-gap Si-Ge-C superlattices. This talk will report on this collaboration with Silvaco.
Emerging WBG/UWBG Power Semiconductor Devices: Silvaco TCAD Enabled Designs and Applications
Dr. Yuhao Zhang
Assistant Professor, Center for Power Electronics Systems, Virginia Tech
Abstract
In the last decade, the landscape of the $40 billion power electronics industry has been reshaped with the production and application of power devices based on wide-bandgap (WBG) semiconductors. This talk will present an overview of WBG and UWBG power devices, as well as our continued, multifaceted use of Silvaco TCAD in the design, analysis and application of WBG/UWBG power devices since 2013. Success TCAD stories to be shared in this talk will include: 3-D simulation for the design of GaN FinFET and tri-gate power devices, simulation for fabrication process optimization, self-consistent electrothermal simulation for power performance evaluation, device-circuit mixed-mode simulation for studying the device dynamics in power circuits, as well as the mixed-mode simulation for understanding the device reliability and ruggedness. The talk will conclude with the perspectives on the future needs of TCAD for power device development.
Modeling Spin Transfer Torque Magnetoresistive Memory
Dr. Viktor Sverdlov
Director, Institute for Microelectronics, TU Wien
Abstract
Emerging spin-based nonvolatile magnetoresistive random access memories (MRAM) are electrically addressable, possess a simple structure, and offer endurance and speed superior to those of flash memory. To facilitate the development of emerging MRAM devices, we are devising a high performance finite element-method (FEM) based simulation approach. In particular, we are developing and implementing a three-dimensional self-consistent simulation tool to evaluate the spin accumulation, torques, and magnetization dynamics in magnetic structures including tunnel junctions. Efficient methods for calculating (i) the demagnetization field, (ii) coupled three-dimensional charge and spin transport trough a textured magnetic structure to evaluate (iii) spin-transfer torques driving (iv) the magnetization dynamics and switching are demonstrated.
A Comprehensive TCAD Model for Oxide-Based ReRAM
Wolfgang Goes
Sr. Development Engineer, Silvaco, Inc.
Abstract
During the last years, the concept of resistive switching has attracted increasing industrial interest and new ReRAM technologies, such as Ag-GeSe3-Ni Conductive Bridge Random Access Memory (CBRAM), have emerged as promising candidates due to their low power consumption, high endurance, and fast switching times. To improve the understanding of these devices, TCAD simulations can be used to study the chemical processes behind the resistive switching. They allow identification of the key factors controlling the switching behavior and can significantly shorten the industrial development schedules. We will present a comprehensive but also flexible ReRAM model, based on our Chemistry Module in Silvaco’s device simulator Victory Device.
State-of-the-art Quantum Transport Simulation with NEMO5 & Victory Atomistic
Dr. Tillmann Kubis
Research Assistant Professor in Network for Computational Nanotechnology at Purdue University
Abstract
This presentation highlights the latest atomistic quantum transport features of NEMO5 and its commercial version Victory Atomistic. NEMO5/VA covers scattering on phonons and charged impurities in group IV and III-V semiconductors. The scattering models quantitatively agree with experimental band gap narrowing and Urbach tails without adjusting parameters. Remote scattering on oxide phonons is found to heavily influence charge transport in transition metal dichalcogenides based devices. While state-of-the-art quantum transport tools suffer from high numerical load and resulting severe limitations to the included physics, NEMO5/VA offers all presented features to a modest numerical load, as detailed in the presentation as well.
Physical Process TCAD: Victory Process’ Crystal Anisotropy Engine
Alexander Toifl
Doctoral student in process TCAD, Institute for Microelectronics, TU Wien
Abstract
Oxide-based ReRAM is an emerging memory technology that combines the advantages of both RAM and Flash technologies. With the increasing demand for big data, artificial intelligence, and neuromorphic computing, ReRAM will play an important role in meeting future memory requirements. For optimizing this technology, predictive and physics-based TCAD simulations are vital as they can dramatically speed up the design, fabrication, and commercial use of new microelectronic technologies through the elimination of expensive and time-consuming experimental test wafers during technology adoption. Therefore, we have developed a comprehensive TCAD model which can be used to study the chemical processes behind the resistive switching. Furthermore, it also allows to analyze a variety of experimental features, such as the resistive switching, the data retention, the current run-away, and the impact of the current compliance. This comprehensive ReRAM model, based on the flexible framework of Chemistry Module, has been implemented in Silvaco’s Victory Device simulator.
Design IP Solutions Update
Jeff Elias
VP & GM, IP Division, Silvaco Inc
Abstract
Mr. Elias will give the update for Design IP and its direction for the future, including new product introductions, acquisitions and partnerships.
Reducing the Layout Development Cycle Time for Standard Cells
Sharmistha Sinha
Sr. Design Engineer, STMicroelectronic
Anand Kumar Mishra
Sr. Managers, STMicroelectronic
Abstract
As semiconductor industry is evolving, product turnaround time must be reduced while ensuring high quality, reliability and profitability. This requirement translates to standard cell layout development cycle time reduction without compromising the robustness, density and manufacturability. Here we present CELLO which is a platform for creating and optimizing standard cell libraries. It includes a layout optimization engine, a built-in Tcl interpreter with a scripting API, distributed jobs support, and export of backend views. Starting from Layout creation from the schematic, it can ease designer’s life for improvement, migration and validation of layouts. These features are easily integrable inside the conventional layout development framework and enable layout engineers to design standard cell layouts faster.
In this paper, we would be sharing the analysis done at ST on multiple technologies for the evolution of the tool. Based on this study, we identified scope to improve the overall efficiency, which were discussed with and implemented by CELLO team. Final result shows that we can save approximately 40% efforts for layout development from scratch by using CELLO.
Functional Safety in Automotive Systems, an NXP Perspective
Kavya Prabha Divakarla
Automotive Systems Functional Safety Architect, NXP Semiconductors
Abstract
As the automotive industry is making a paradigm shift towards more Automated Vehicles, the evolution of Functional Safety concepts is becoming more evident. This session by NXP will focus on introducing the evolving Functional Safety trends in the automotive market in addition to describing how NXP tailors the ISO 26262 implementation of Functional Safety within the organization. A walkthrough of IP integration process into the SoC will also be provided.
Speed Up Wireless IOT SOC Implementation by using Silvaco AHB Performance Subsystem IP
Ken Li
Vice-President, Rafael Microelectronics, Inc.
Cashew Chen
Vice President, Rafael Microelectronics, Inc.
Abstract
To maintain our highly efficient design cycle for designing time-consuming basic digital blocks for SOC, and allow our designers spend valuable time on critical wireless subsystem design and details, Rafael Microelectronics adopt Silvaco’s AHB Performance subsystem IP to speed up our design process, especially on PMU, Memory management and interface periphery.
SoC Security Trends and Samsung Security IPs
Jonghoon Shin
Principal Engineer, Samsung Foundry
Abstract
Various attack techniques that violate the security and safety of SoC are developed day by day, and the techniques are becoming more sophisticated. For example, previous side channel analysis found out secret information by analyzing the correlation between security information and power consumption pattern or operation time difference, but recently, it has evolved to an analysis technique for cache hit/miss behavior or electromagnetic characteristics. In addition, it has also been combined with malware or fault injection method. Due to this trend, mobile, automotive and IoT products have to equip secure and cost-effective attack countermeasures and protection method, even if they are not security products such as Smart Card. In this presentation, you can find various kinds of attack to SoC product and Samsung Security IP/solution to prevent them in SoC.
Optimized Applications for NXP CoolFlux DSP Ultra-low Power Programmable Cores
Johan Van Ginderdeuren
Director, IP Blocks Licensing, NXP Semiconductors
Abstract
Mr. Van Ginderdeuren will present on NXP's ultra-low power CoolFLux DSP for digital audio, software defined radio, wireline processing, and intelligent sensor processing applications.
TCAD Simulation Update
Dr. Eric Guichard
VP & GM, TCAD Division, Silvaco Inc
Abstract
Mr. Guichard will give the update for Silvaco TCAD simulation and the direction of future development.
Farhad Hayat
VP of Global Marketing
Farhad Hayat is Vice President of Global Marketing chartered with defining, driving, and promoting Silvaco’s leadership in the TCAD, Custom IC and IP markets. Key areas of responsibility include strategic planning, corporate marketing, product marketing, market research, brand management, corporate communications, and ecosystem alliance programs.
Farhad joined Silvaco in January 2020 with 20+ years of experience in strategic marketing, corporate communication, product management and business development in Electronic Design Automation market. Most recently he led marketing at Synopsys for Analog/Mixed-signal simulation and Custom IC design products. Before that he held various senior marketing positions at LogicVision, Synopsys and Cadence.
Farhad holds a BSEE and MSEE from university of Tulsa, Oklahoma.
Babak Taheri
CEO/CTO, Silvaco Inc
Babak Taheri is the CEO at Silvaco Inc., a leading provider of TCAD, EDA, and design IP software. He began his career at Silvaco as chief technical officer and executive vice-president of products. Previously, he was the CEO / president of IBT working with investors, private equity firms, and startups on M&A, technology, and business diligence.
While at IBT, he served on advisory boards of MEMS World Summit, Novasentis, AGCM, ALEA labs, Lion Point Capital, and Silver Lake. Prior to IBT, he was the VP & GM of the sensor solutions division at Freescale semiconductor (now NXP).
Babak was the recipient of ”the perfect project award” in 2003 while at Cypress; Twice recipient of the “Diamond Chip Award” in 2013 /14 while at Freescale; recipient of the MEMS & Sensors executive of the year award in 2014, and in 2015 was the recipient of the Distinguished Engineering Alumni Medal from UC. Davis College of Engineering, where he is on the advisory board to the college.
He also held VP/GM roles at Cypress Semiconductors, Invensense (now TDK) and key roles at SRI International and Apple. He received his Ph.D. in biomedical engineering from UC Davis with majors in EECS and Neurosciences, has over 20 published articles and holds 28 issued patents.
Thomas Blaesi
VP & GM, EDA Division, Silvaco Inc
Thomas F. Blaesi is Vice President and General Manager of the EDA Business Unit. He is responsible for managing the development of all EDA tools including analog custom design, circuit simulation and SPICE modeling. Thomas joined Silvaco in October 2017 and held the position of Vice President of Global Marketing until December 2019. He has more than 25 years of experience in corporate strategy, business development, and marketing in semiconductor, and electronic design automation industries.
Bogdan Tudor
Senior Manager, Device Characterization, Silvaco Inc
Bogdan Tudor is Head of Device Characterization for Silvaco, leading the Utmost and Modeling Service teams. He has over 20 years of experience in model development and characterization software.
Jody Matos
Senior Manager Simulation, Silvaco Inc
Jody Maick Matos is a Senior Manager at Silvaco, Inc. In this position, he has been managing leading-edge R&D and business-related projects for EDA tools. His current tasks are mainly related to SPICE simulation, power, EM/IR and thermal analysis on analog, digital and mixed-signal IC designs.
Fred Sendig
Vice President of R&D, Silvaco Inc
Fred Sendig leads R&D of Silvaco’s Analog Custom Design Division. He is responsible for driving the business and development efforts for custom design, physical realization, verification, PDK development and services. He brings nearly 35 years of experience in EDA and CAD to Silvaco having previously held positions of VP CAD and Methodology at Altera, Fellow/VP of R&D at Synopsys and R&D Fellow at Cadence.
Jon Sanders
Director of Product Engineering, Silvaco Inc
Jon Sanders leads the corporate application engineering (CAE) and process design kit (PDK) teams in the EDA division. He has held leading engineering director and managament roles at both Synopys and Cadence Design Systems since the 1990s.
Dr. Alex Samoylov
Senior Manager, EM/IR Analysis, Silvaco Inc
Alex Samoylov, has over 20 years of experience in the physical implementation area including power, timing, and reliability analysis for standard cell and transistor level designs.
Dr. Eric Guichard
VP & GM, TCAD Division, Silvaco Inc.
Dr. Eric Guichard is Vice President of Silvaco’s TCAD Division. He is responsible for managing all aspects of the TCAD division from R&D to field operations. Since joining Silvaco in 1995, he has held numerous positions including director of Silvaco France and most recently Director of Worldwide TCAD Field Operations. Prior to joining Silvaco, Guichard was a senior SOI engineer specializing in transistor and circuit aging at LETI and Thomson Military and Space.
Dr. Guichard holds an MS in material science and a Ph.D in semiconductor physics from Ecole Nationale Polytechnique de Grenoble, France.
Carlos Augusto, Ph.D.
Co-Founder and CTO, Quantum Semiconductor
Dr. Augusto is a co-founder and the Chief Technology Officer of Quantum Semiconductor. A prolific inventor, he is responsible for Quantum Semiconductor’s core technology. Dr. Augusto has been in the semiconductor industry for 20 years. Carlos has a BSc. in Physics from the Instituto Superior Técnico, Technical University of Lisbon, Portugal, M.S. in Physics of Microelectronics and Materials Science, and Ph.D. in Electrical Engineering with a specialty in device physics from the Catholic University of Leuven, Belgium. He is the author or co-author of 27 patents in image-sensors, advanced silicon devices, light-valves, optical communications, and solar cells.
Dr. Yuhao Zhang
Assistant Professor, Center for Power Electronics Systems, Virginia Tech
Dr. Yuhao Zhang is an assistant professor with the Center for Power Electronics Systems (CPES) at Virginia Tech. Before joining CPES, he worked as a postdoctoral associate at Massachusetts Institute of Technology (MIT) from 2017 to 2018. He received his Ph. D. and S. M., both in electrical engineering from MIT in 2017 and 2013, respectively. Prior to joining MIT, he received his B. S. in physics from Peking University in 2011 with the highest honor. He received the MIT Microsystems Technology Laboratories Doctoral Dissertation Award in Spring 2017 and the IEEE George Smith Award in 2019. His research interest is at the intersection of power electronics, micro/nano-electronic devices, and advanced semiconductor materials.
Dr. Viktor Sverdlov
Director, Institute for Microelectronics, TU Wien
Viktor Sverdlov is currently heading the Christian Doppler Laboratory for Nonvolatile Magnetoresistive Memory and Logic at the Institute for Microelectronics, TU Wien, Austria. His research interests include device simulations, computational physics, solid-state physics, spintronics and nanoelectronics. Viktor holds his Master’s and PhD degrees in Theoretical Physics from the State University of Leningrad/St.Petersburg, and his Habilitation in Microelectronics from TU Wien. Viktor worked as a staff research scientist at the V.A.Fock Institute of Physics, State University of St.Petersburg, Université de Genève, University of Oulu, Helsinki (Aalto) University of Technology, Freie Universtät Berlin, and State University of New York at Stony Brook before he joined the Institute for Microelectronics, Technische Universität Wien, in 2004.
Wolfgang Goes
Sr. Development Engineer, Silvaco Inc.
Dr. Wolfgang Goes is a development engineer in Silvaco’s TCAD Division. Since joining Silvaco in 2016, he has worked primarily on Victory Device but also on Atlas and is responsible for reliability issues and memory technologies. Dr. Goes holds an MSc in Technical Physics and a PhD in Electrical Engineering, both from the TU Vienna. He continued working there as a post-doc at the Institute for Microelectronics focusing on reliability issues in microelectronic devices.
Dr. Tillmann Kubis
Research Assistant Professor in Network for Computational Nanotechnology at Purdue University
Prof. Dr. Tillmann Kubis is leader of Purdue’s NEMO5 development team. His research interest includes all topics of equilibrium and non-equilibrium phenomena in nanodevices and molecules. This covers electronic and phonon bandstructures as well as heat, charge and spin transport in nanodevices. Dr. Kubis holds a Dr. rer. nat. in theoretical semiconductor physics from the Technische Universität München, Garching, Germany.
Alexander Toifl
Doctoral student in process TCAD, Institute for Microelectronics, TU Wien
Alexander Toifl is currently pursuing a doctoral degree in the area of process TCAD with the Christian Doppler Laboratory for High Performance at the Institute for Microelectronics, TU Wien, Austria. His research interests include anisotropic etching and epitaxy of nonplanar three-dimensional topographies and post-implantation annealing of SiC and GaN. Alexander Toifl holds a Bachelor's degree in Electrical Engineering and a Master's degree in Microelectronics and Photonics from TU Wien.
Richard Trihy
Vice President of Engineering, Design Enablement, GLOBALFOUNDRIES
Richard Trihy is Vice President Design Enablement at GLOBALFOUNDRIES where he is responsible for the delivery of EDA enablement (including Process Design Kits, Compact Models and Design Methodology) for all Semiconductor design platforms at GLOBALFOUNDRIES. Richard joined GLOBALFOUNDRIES in 2009. Prior to GLOBALFOUNDRIES Richard held R&D leadership roles in EDA at Synopsys and Cadence. Richard received his B.E. and M.Eng.Sc degrees in Electrical Engineering from University College Cork, Ireland and his Ph.D in Electrical and Computer Engineering from Carnegie Mellon University Pittsburgh PA.
Gurtej Sandhu
Senior Fellow and Vice President, Micron Technology
Gurtej Sandhu is Senior Fellow and Vice President at Micron Technology. In his current role, he is responsible for Micron’s end-to-end (Si-to-Package) R&D technology roadmaps. The scope includes driving cross-functional alignment across various departments and business units to proactively identify technology gaps, and managing the engineering organization to resource and execute on developing innovative technology solutions for future memory scaling. Dr. Sandhu’s responsibilities include leading several internal project teams worldwide and managing interactions with research consortia around the world. Dr. Sandhu received a degree in electrical engineering at the Indian Institute of Technology, New Delhi, and a Ph.D. in physics at the University of North Carolina, Chapel Hill, in 1990. He holds over 1,300 U.S. patents and is recognized as one of the top inventors in the world. Dr. Sandhu is a Fellow of IEEE. In 2018, he received the IEEE Andrew S. Grove Award for outstanding contributions to silicon CMOS process technology that enables DRAM and NAND memory chip scaling.
Rahul Goyal
Vice President and Director of R&D Strategic Enablement, Intel
Goyal has global responsibility at Intel for strategic sourcing, supply chain strategy, strategic collaborations, ecosystem enablement, data analytics, and capacity management related to product development across Intel’s broad product portfolio. This includes software, system and semiconductor intellectual property, product development outsourcing services, electronic measurement solutions, electronic design automation software, prototyping and verification products used in all aspects of product design, validation and technology development. Goyal joined Intel in 1989 and has held various technical and management positions in software engineering and technology development. Goyal holds a bachelor’s degree in electrical and electronics engineering from Birla Institute of Technology and Science in Pilani, India, and a master’s degree in computer engineering from Syracuse University in New York.
Jonghoon Shin
Principal Engineer, Samsung Foundry
Jonghoon Shin is a Principal Engineer at Samsung Foundry and responsible for Security IP design in IP development team.
He is engaged in the development of security and crypto hardware for various products such as mobile, automotive, IoT and smart card.
His research interests include SoC security architecture, crypto algorithm acceleration, public key cryptosystem application, and secure implementation against side channel attack.
Jonghoon Shin received his B.S, M.S. and Ph.D. degrees in electrical engineering from POSTECH, Pohang, Korea.
Ken Li
Vice-President, Rafael Microelectronics Inc.
Following Ken’s first career at Altera (USA) in 1988 as circuit designer. , Ken worked for National Semiconductor(USA) and S3 Graphics (USA), responsible for Video/Graphic related mixed signal blocks design and COT management. In 2005, Ken co-founded Tenor Electronics (Taiwan/Beijing/USA) with focus on mobile audio codec and DAB IC developments. Tenor was acquired by AIT (Alpha-Imaging Technology, Taiwan) in 2007. Ken devoted himself on high performance audio codec, MIPI, HDMI and USB interface IP during 5 years of stay at AIT. In 2011, Ken founded Analog Chip Corp. (Beijing) with IP and SOC design service business. Ken left Analog Chip in 2015 and Joined Brite semiconductor (Shanghai) as Vice President of IP development. In 2017, Ken joined Rafael Microelectronics as Vice President to head IOT wireless Business Unit.
Ken received his BSEE from National Chiao-Tung University in 1984 and MSEE from Portland State University in 1988.
Cashew Chen
Vice-President, Rafael Microelectronics Inc.
Cashew joined Accton (Taiwan), a leading data center and enterprise switch company, in 1988 and worked in Accton for 20 years as Corporate VP before he joined Ralink, a WiFi/BT IC design company, in 2008 as VP of System Design. Cashew joined Mediatek Wireless Connectivity BU (WCN) following MTK’s acquisition of Ralink in 2010, dedicated to WiFi/BT system design and customer applications. He also work for Nephos, a Mediatek Subsidiary designing 6.4T switch silicon as Business Development VP before he joined Vertexcom as Marketing VP promoting PLC/Sub-Ghz dual-mesh based multi-protocol IOT applications in 2017. In 2019 Cashew Joined Rafael Micro as VP and head of Optical Communication BU.
Cashew received his BSEE from National Cheng-Kung University (Taiwan) in 1986 and MSEE from University of Maryland (USA) in 1992. He also received EMBA from National Cheng-Kung University (Taiwan) in 2001.
Sharmistha Sinha
Senior Design Engineer, ST Microelectronics
Sharmistha Sinha is a Senior Design Engineer at ST Microelectronics. She has 5 years of experience in Standard Cell domain in Semiconductor industry. She is working with STM from almost past 3 years. She has worked with NXP and Maxim before joining STM. She has a master’s degree in VLSI from Amity University, Noida.
Jeff Elias
VP & GM, IP Division, Silvaco, Inc.
Jeff Elias is responsible for managing all semiconductor design IP business at Silvaco including relationships with foundries and other IP partners. He joined Silvaco in June 2017 as a business advisor before taking on his current role in December 2019. He has more than 20 years of global experience in semiconductors, systems, and software as a sales and marketing executive, with positions at Transpacific IP Group, Spin Transfer Technologies, FSA Technologies, SIVRAL, Foveon, and MOSAID.
Jeff holds a BSEE from the University of Michigan and an MBA from the Leavy School of Business, Santa Clara University.
津村 明宏 様
株式会社産業タイムズ社 電子デバイス産業新聞 編集部 編集長
1995年3月 関西大学 経済学部卒。1999年3月 株式会社産業タイムズ社に入社。電子デバイス業界の専門紙である電子デバイス産業新聞（旧・半導体産業新聞）の記者として、2007年より副編集長、2009年12月より編集長。
Anand Kumar Mishra
Senior Manager, ST Microelectronics
Anand Kumar Mishra graduated from Institute of technology Banaras Hindu University (now IIT-BHU) in 2001. He worked for SRAM development in ST for 16 years before joining standard cell development team. His topics of interest are high density SRAM, standard cell for low power applications and process monitoring structures.
He is currently serving as senior Manager in Standard cell development team at ST Microelectronics PVT Ltd Noida.
Firas Mohamed
VP Advanced R&D & GM Silvaco France
Dr. Firas Mohamed will give his perspective on the means to achieve practical simulation and Monte Carlo analysis of full-chip analog and memory designs.
Simon-Alexis Abric
Corporate Application Engineer
Mr. Simon-Alexis Abric is a Corporate Application Engineer for Silvaco France. He is responsible for customer technical support for reduction (Jivaro) and parasitic analysis (Alps) products. Mr. Abric earned a Master of Engineering degree in integrated circuits and systems in 2013 from the engineering school ENSEIRB in Bordeaux, France.
Jean-Baptiste Duluc
Senior Corporate Application Engineer
Dr. Jean Baptiste Duluc is the core-competency application engineer in charge of VarMan product development at Silvaco. He joined Silvaco in 1999 as support engineer for the characterization and modeling software Utmost. Dr. Duluc holds a MS and PhD in microelectronics from the University of Bordeaux, France.
Kavya Prabha Divakarla
Automotive Systems Functional Safety Architect, NXP Semiconductors
Dr. Divakarla has been with NXP since 2017 working within the Microcontroller and Microprocessor business line in the Automotive Business Unit. In her current role as the Functional Safety Architect/ Manager, she is focused on the Functional Safety for Autonomous, Vision and Gateway products. She received her B.Tech. degree in Process Automation Technology in 2012 and M.A.Sc. and Ph.D. in Electrical and Computer Engineering in 2014 and 2018 respectively from McMaster University, Canada.
Johan Van Ginderdeuren
Director, IP Blocks Licensing, NXP Semiconductors
Mr. Van Ginderdeuren will present on NXP's ultra-low power CoolFLux DSP for digital audio, software defined radio, wireline processing, and intelligent sensor processing applications.
Jin Jang
Director of the Advanced Display Research Center
Jin Jang is a Professor at Department of Information Display of Kyung Hee University. His current research programs are in oxide and LTPS TFTs for displays, TFT circuits and TFT application to sensors, QLED, Micro-LED and flexible AMOLED. He is the author or co-author of over 1,000 technical publications of which over 600 are in SCI Journals such as Nature, Advanced Materials, Advanced Functional Materials, Energy Environmental Science, APL, IEEE TED and IEEE EDL. He is currently a Director of Advanced Display Research Center (ADRC) and had served as Program Chair of SID Symposium 2007 and General Chair of SID Display Week in 2009 and General Chair of IMID 2012, 2013. He is a Fellow of SID and he was awarded George Smith Award from IEEE in 2012, Slotto Owaki Prize from SID in 2015 and Ho-Am Award in 2017.
Jeong-Ik Lee
Assistant Vice President Reality Devices Research Division
Jeong-Ik Lee received his B.S., M.S., and Ph.D. Chemistry degrees from Korea Advanced Institute of Science and Technology (KAIST) in Daejeon, South Korea in 1992, 1994, and 1997, respectively. After graduating, he joined IBM Almaden Research Center in San Jose, CA, USA as a postdoctoral associate, and worked on OLED materials. He joined ETRI in 1999 and continued his research on OLED materials and devices. He has led the Reality Devices Research Division of ETRI since 2017 and has worked on the convergence of display and sensor technologies.
Sharon Fang
VP & GM, Silvaco China
Sharon Fang is a seasoned executive with a distinctive combination of sales, marketing, strategic thinking and operational skills, successful track record and driving revenue growth as both an individual contributor and sales manager in EDA. Sharon currently serves as General Manager for Silvaco China. In her role as head of China region, Sharon is putting together the necessary processes and infrastructure to streamline the sales process, empowering individuals and teams to maximize value to customer as well as ROI. The China organization is focused on helping drive customer success through the use of Silvaco TCAD-to-sign off solutions, modeling services, IP management & compliance software while driving business growth for the company.
Sharon holds a bachelor of Art degree from Southwest China Normal University and an MBA degree from Saint Mary’s College of California.
Dan Jiang
Application Engineer, Silvaco China, Ltd
Dan Jiang is responsible for the EDA tools supporting in Silvaco China. He has more than 10 years of experience in design， EDA tools validation and project CAD. She received her B.E. from SiChuan university.
Kevin Chang
TCAD Application Engineer Manager, Silvaco China Co. Ltd
Kevin Chang is a TCAD application engineer manager in Silvaco China, has worked in the TCAD area of the semiconductor and display market for more than 10 years, and has lots of experience supporting customer success in process and device simulation and 3D physical parasitic extraction tools.
Ke Liu
Application Engineer Manager, Silvaco China, Ltd
Ke Liu is responsible for the EDA tools supporting in Silvaco China. He has more than 10 years of experience in simulation division. He received his M.S Microelectronics from NUDT.
Takeshi Kuwagagi
APAC FAE manager, Silvaco Japan
Takeshi Kuwagaki received the B.S. degree from applied physics engineering from Osaka City University, Osaka, Japan, in 1994. He joined Silvaco Japan Co,. Ltd., Yokohama, Japan, in 1997 as an application engineer to be engaged in customer and software development supports of layout design, design verification, and parasitic extraction tools. Now he is Engineering Manager in SILVACO Japan, and APAC FAE manager.