• Interface PHYs

Silvaco IP offers production-proven high-speed interface IP solutions for Samsung Foundry. Items marked AQ are AEC-Q100 qualified and ASIL assessed for automotive applications.

ProtocolFeatures
Samsung Foundry
28nm
FD-SOI
14 nm
11 nm
10 nm
8 nm
7 nm
5 nm*
PCIePCIe Gen 3, 8 Gbps
PDF AQ
PDF
PCIe Gen 3/4, 16 Gbps
PDF
PDF AQPDF

PDF AQ
DDRDDR3/4, 3.2 Gbps, 32/64-bitPDF AQ
PDF
PDF AQ
LPDDR3/4, 4.3 Gbps, 16/32-bitPDF AQ
PDF
PDF AQ
DDR/LPDDR3 Combo, 1.6 Gbps, 32-bit
PDF
PDF
LPDDR4/4X, 4.3 Gbps, 16/32-bit
PDF
PDF
PDF
PDF AQ
LPDDR4/4X/5, 5.5 Gbps, 16-bit
PDF AQ
LPDDR4/4X/5, 6.4 Gbps, 16-bit
PDF
PDF AQ
PDF
PDF AQ
HBM2e, 3.2 Gbps

AQ

MIPIM-PHY G3, 6.0 Gbps (UFS only)
PDF
PDF
PDF
PDF AQ
M-PHY G4, 12.0 Gbps (UFS only)
PDF AQ
PDF
PDF AQ
PDF
PDF AQ
D-PHY V1.2, 2.1 Gbps
PDF
PDF
C-PHY D-PHY Combo V1.1 (2.5 Gbps) / V1.2 (2.5 Gbps)
PDF AQ
C-PHY D-PHY Combo V1.1 (2.5 Gbps) / V2.0 (4.5 Gbps)
PDF
PDF AQ
PDF
PDF AQ

SerDesSerDes 56 Gbps, 10/50G-KR, 100G-KR2/4, 200G-KR4
PDF
PDF
HDMIHDMI 2.0 Tx, 6.0 Gbps
PDF
PDF
USB / DisplayPort ComboUSB 3.1 Gen 1 / DP Tx Combo, 5 Gbps / 5.4 Gbps
PDF
PDF AQ
PDF

PDF AQ
V-by-OneTx, 4 Gbps, 16 lanes
PDF
PDF
Rx, 4 Gbps, 8 lanes
PDF
PDF

*ASIL assessment is underway and scheduled to be completed.

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High speed Interface Design: Best Practices

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Customers

Srinath Anantharaman
 The integrated solution enables design teams to collaborate efficiently in a secure design environment when developing their IPs or SoCs either locally or across multiple design sites. It enables design teams to successfully tapeout their designs by mitigating the risk by sharing and using the correct version of the design data and IPs. 
Rick Lazansky
 Over the past two years, Silicon Catalyst has been working with key industry players to develop a complete ecosystem that economically and effectively supports the new wave of semiconductor startups that we are seeing today. Our Portfolio Companies have consistently been requesting IP as the critical element that we had not been able to deliver. Silvaco’s offering fulfills a real hole that has been impeding the success of these startups. We are glad to deliver this capability as we continue to build the semiconductor start up ecosystem.