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Layout Engineer, Memory IP Team

Location: Grenoble – France, United Kingdom – St Ives, or Remote

Overview

Silvaco is a leading EDA tools and semiconductor IP provider used for process and device development for advanced semiconductors, power IC, display, and memory design. For over 30 years, Silvaco has enabled its customers to develop next generation semiconductor products in the shortest time with reduced cost. We are a technology company outpacing the EDA industry by delivering innovative smart silicon solutions to meet the world’s ever-growing demand for mobile intelligent computing. The company is headquartered in Santa Clara, California and has a global presence with offices located in North America, Europe, Japan, and Asia.

Silvaco is a privately held company, measuring itself to the highest ethical standards and world class performance.

Position Description and Responsibilities

As a Layout Engineer in our France, Alps based Memory IP Team, you will be contributing to all the layout and foundry related aspects of our state-of-the-art Memory Compiler Products. From the development of new compilers to the enhancement and maintenance of the existing ones, you will also be working on the back-end memory development and verification flows, as well as maintaining and updating the different back-end automation scripts that are also essential parts of the activity.

Responsibilities include:

  • Layout implementation experience and following required specifications
  • A good understanding of memory compiler architectures and sub-blocks
  • Experience or good knowledge in FinFET is a plus
  • Experience driving circuit layout reviews with designers
  • A good understanding of LVS, DRC and ERC reports and be able to make the necessary corrections (Calibre)
  • Worked in collaboration with designers to find the best design/layout compromises
  • Experience delivering quality work in a timely when under pressure
  • Knowledge of scripting is a plus (shell, skill, tcl)
  • Knowledge of SLAM or Expert is a plus

Desirable Qualifications

  • 5+ years of memory layout experience in the development of low power, high-performance, high-density SRAM/DPRAM/ROM memories
  • Excellent organizational, prioritization, time management skills and an unwavering commitment to integrity and professionalism
  • Self-starter and strong closer with multitasking ability
  • Language: French with good spoken and written English
  • Working knowledge of Microsoft PowerPoint and Excel (including operations such as v-lookup, functions, pivot tables, etc.)

Click here to apply (UK).
Click here to apply (France).