Simulate 40X Faster with SmartSpice HPP
As technology advances, the complexity of circuit designs is continuously growing, whereas the design cycles become even shorter. Consequently, circuit simulation can easily become the bottleneck for design verification. An analog simulator, therefore, must deal with a larger number of advanced devices, while still maintaining the same level of accuracy for a given simulation time.
In order to cope with this increasing pressure on the simulator’s performance, SmartSpice has introduced a new simulation engine: HPP (High Performance Parallel). SmartSpice HPP takes advantage of the modern multicore hardware platforms to speed up all internal aspects of transient simulations of analog circuits.
One of the main differences of SmartSpice in HPP mode is its partition-based simulation, where partitions will be processed in parallel and the matrix loading stage, linear solver operations, as well as general transient simulation steps are sped up. Further improvements can also be achieved when the block isomorphism and block latency features are enabled. Finally, one can extract the most out of SmartSpice HPP for post-layout simulation when it is used in conjunction with Jivaro for parasitic reduction.
In this application note, we describe SmartSpice HPP, how it works, and how to use it in order to provide fast and accurate transient simulations on a variety of designs, from medium- to large-size circuits, either pre- or post-layout. We also demonstrate in this application note multiple usage modes, so one can see that SmartSpice HPP can not only be up to 8x more scalable than regular SmartSpice, but it can also be up to 40x faster, while still keeping acceptable accuracy.
Follow the link to read the rest of the SmartSpice HPP: High Performance Parallel with SPICE Accuracy application note.
Be sure to register for the upcoming Silvaco webinar on SmartSpice HPP taking place on November 17. To register, go to Webinar on Simulate 40X Faster with SmartSpice HPP.