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230 Papers on Power Device Simulations using Silvaco TCAD

A quick search of the IEEE Xplore online library gives a list of more than 230 published technical articles on Power Device Simulation using Silvaco TCAD. Here are some recent papers with the authors’ abstracts that cover silicon-carbide (SiC) and Junction-Less Double Gate MOSFET devices. Any mention of ‘we’ or ‘our’ refers to the paper’s authors:

Advanced Materials and New Architectures for AI Applications

Over the past 50 years in our industry, there have been three invariant principles: Moore’s Law drives the pace of Si technology scaling system memory utilizes MOS devices (for SRAM and DRAM) computation relies upon the “von Neumann” architecture

Everything You Want to Know about Silvaco Foundation IP

In the creation of an ASIC or SoC a wide variety of digital components are needed. Standard logic cells are used to implement the high-level description of the chip which is typically written in RTL. A synthesis tool such as Design Compiler or RTL Compiler is used to generate a gate-level netlist built out of the standard logic cells from a cell library. Communication on and off of the chip, requires unique input/output cells or I/Os that can drive off-chip wiring and withstand electrostatic discharges in the range of thousands of volts. The other main category is digital memories typically SRAMS that can take up a significant amount of area on the die for a chip. These 3 categories of digital design IP are called Foundation IP.

System and Method for IP Fingerprinting and IP DNA Analysis

In the world of SoC development, an IP management system is software for the licensing, distribution and compliance administration of design IP for both vendors and consumers of IP. In May 2019 Silvaco was awarded a patent for System and Method for IP fingerprinting and IP DNA analysis. This patent reflects the unique technology inside the Xena® IP Management System from Silvaco.

Machine Learning in Silvaco EDA Software

In the following video, Dr. Firas Mohamed, VP & GM, Machine Learning & Flow Optimization Division and GM, Silvaco France talks with Graham Bell about Machine Learning technologies deployed in Silvaco EDA tools at the SEMICON West 2019, July 9 - 11 at Moscone Center in San Francisco. A transcript of the video is also below.

I/O Design and Characterization – How Can You Compete with Free?

I interviewed Silvaco partner Stephen Fairbanks, CTO of Certus Semiconductor from the show floor at DAC 2019, in Las Vegas, about I/O Design and Characterization. He talks about using the Viola characterization tool from Silvaco for a complex part while under time pressure to produce an accurate model. A full ranscript of the conversation is below.

Talking Atoms to Systems in Next-Generation SoC Designs

New system-on-chip (SoC) devices are driving new memory architectures and photonic interfaces, while specialized new intellectual property (IP) requires analysis down to the nanometer and atomic levels because of single nanometer process nodes. According to Babak Taheri, CTO and EVP of products at Silvaco, a leading EDA Software, semiconductor IP company, a member of SEMI and the ESD Alliance, a SEMI Strategic Association Partner, design technology co-optimization and proven IP are required for this analysis.

5nm Success – Silicon Creations CEO Video Interview at DAC 2019

In the following video, I interview Silvaco customer Randy Caplan of Silicon Creations from the show floor at DAC 2019, in Las Vegas, about the latest trends and challenges for nanometer IC design success. He talks about using a suite of Silvaco design tools down to the latest 5 nm silicon process nodes. A full ranscript of the conversation is below, as well.

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