High Voltage Power Device Modeling with HiSIM_HV 2
This webinar will provide a comprehensive overview of model parameter extraction for high voltage devices, using the industry standard HiSIM_HV 2 model. HiSIM_HV 2 model parameter effects will be explained first, followed by a step-by-step description of model parameter extraction using Utmost IV. Finally, depletion mode, which is implemented in the latest version of HiSIM_HV 2.2.0 will be introduced.
What attendees will learn:
- Device structures and the electrical characteristics: MOS, LDMOS, HVMOS, Extended Drain MOS (XDMOS)
- Release history of HiSIM_HV models: HiSIM_HV 1.2.0, 2.1.0 and 2.2.0
- HiSIM_HV 2 model review: HiSIM 2 core and the quasi 2-D resistor model
- HiSIM_HV 2 model extraction flow
- New depletion mode in HiSIM_HV 2.2.0
Presenter
Yoshihisa Iino is a Staff Engineer at Silvaco Japan and has been employed at the company for 20 years. Since then, he has been in charge of the Utmost device characterization and SPICE modeling product. Prior to joining Silvaco Japan, he worked at a bipolar IC company and was tasked with establishing a CMOS technology development platform which included the use of Silvaco tools. Prior to this he worked at Texas Instruments Japan Limited, where he was a principal characterization engineer for the extended drain MOS device technology and was responsible for defining process conditions and layout design rules.
Yoshihisa Iino received his B.S. degree in electrical engineering under Prof. Katsufusa Shono’s instruction from Sophia University, Tokyo, Japan.
When: March 28, 2015
Where: Online
Time: 10:00am-11:00am-(PST)
Language: Japanese
WHO SHOULD ATTEND:
SPICE modeling engineers for high voltage technology devices and circuit designers who have interest in HiSIM_HV 2