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Device 3D

3D Device Simulator

Device 3D is a physics based 3D device simulator for any device type and includes material properties for the commonly used semiconductor materials in use today. The physical phenomenon that can be simulated self consistently with the semiconductor equations include photon absorption, photon emission, bulk and interface traps, magnetic fields, self heating, ionizing radiation strikes, hot carrier and tunneling effects. This allows simulation of devices such as solar cells, CMOS sensors, LEDs, TFTs, EPROMs, aggressive technology CMOS and power devices. Device 3D uses a simple, intuitive and flexible syntax and runtime environment together with excellent 2D and 3D visualization tools compliment this powerful product.

Nano Scale Devices

Fin FETs, nano wire FETs and standard FETs at aggressive technology nodes all can be simulated using Device3D.

Fin FET

Fin FET example created directly using Device 3D syntax, showing doping electron distribution and IV characteristics using both drift-diffusion and Bohm Quantum Potential 3D models.

Phosphorus concentration for a FinFET device.	Electron concentration showing depletion region under the gate.

Id/Vg characteristics comparing drift-diffusion and Bohm Quantum Potential (BQP) solutions.

Nano Wire FET

A recent addition to the Quantum modeling capability has enabled simulation of the strong quantum confinement effect in quantum wire devices. To model the effects of quantum confinement, Quantum 3D allows a self-consistent solution of the 1D or arbitrary shape 2D Schrodinger and 3D Poisson equations.

Contours of electron wavefunctions on the surface of 3D structures, found by 1D (left) and 2D (right) Schrodinger equation solved self-consistently with 3D Poisson equation.

Device schematic (top left), isosurface of total current density (bottom) and isosurface of electron density (top right) of a 3D silicon nanowire FET with flared-up source and drain regions, computed with coupled mode space NEGF approach.

Schematics (left) and I-V characteristics (right) of a Si nanowire transistor with uniform channel cross-section, computed with uncoupled mode space NEGF approach.

Aggressive Geometry 50nm MOSFET

In this example, the 50nm MOSFET structure was created using “Victory-LD” (Victory Large Device). Victory-LD is a process simulator option that allows creation of Device3D compatible structures following arbitrary shape mask layout driven 3D process simulation.

The mask set, process simulated shape, converted Device 3D structure and electrical characteristics are shown below.

Mask layout	Process simulated structure

Converted ATLAS structure with and without gate spacer.

Cross section of net doping.	IV characteristics for different channel doping.

Quantum Well Analysis

Analysis of bound states and wave functions are possible in 3D quantum devices. Here, analysis for a single quantum well and a triple quantum well design are shown as examples.

SQW Analysis

3QW Analysis

GaN/InGaN/GaN single Quantum Well (QW) and delta sandwiched QW quantization.

Memory Devices

Hot carrier injection and tunnelling models allow the injection of charge on to floating gates, necessary for the simulation of memory devices. An EPROM example is shown below.

EPROM electron concentration	EPROM potential distribution shown as an isosurface plot

IV characteristics before and after programing	Floating gate integrated charge as a function of time

Opto-Electronics

Ray tracing, optical absorption and optically generated carriers are solved self consistently with all other semiconductor equations allowing simulation of light absorbing devices such as photo-diodes and CMOS sensors. Photon generation equations also allow simulation of optically emitting devices such as light emitting diodes (LEDs).

Photodiode Simulation

InP/InGaAsP/InGaAs/InP photo diode	Dark and illuminated anode current versus anode voltage at 1.55µm

CMOS Simulation

Advanced 3D ray tracing capability of Luminous 3D can be used to evaluate spatial resolution and crosstalk issues in imaging arrays	CMOS sensor potential distribution

GaN LED Simulation

Radiative Recombination Rate distributions

Thin Film Transistors

The electrical characteristics of thin film transistors (TFTs) are dominated by the existence of bulk and surface traps. In Device 3D these defects can be described as a continuum of defects throughout the bandgap, or can be specified individually. The insulating substrates that these devices are fabricate on (usually glass), are often poor conductors of heat. The additional modelling of self heating effects can often have a considerable effect on device electrical characteristics.

Octagonal array of TFT elements. The contacts and the SiO2 layers have been made transparent so that the amorphous Si element can be seen more clearly.

Transfer characteristics for a poly-Si TFT.	Id/Vd characteristics with and without lattice temperature modeling.

Power Devices

Understanding the operation of power devices is an excellent application for 3D TCAD device modelling. Power devices, such as thyristors and triacs etc, often have electrical characteristics dominated by semiconductor phenomenon that occurs deep in the bulk silicon of the device which is difficult to probe directly with measurements. 3D TCAD simulation allows analysis of exactly what is going on throughout the whole device and any time instant during switching transients etc. Below is an example of a UMOS HexFET simulation.

Potential distribution for a UMOS HexFET.	Id/Vg characteristics for a UMOS HexFET.

Adding External Circuit Elements

Power devices are often tested and characterized with other connected passive load elements. Here a bipolar transistor is tested with lumped elements attached to it’s terminals.

Mixed device and circuit element simulation

Maximum device temperature and base current as a function of time

Self Heating

A number of power devices heat up considerably during normal operation. Simulation of self heating effects can detect possible hot spots in your design. Here a simple resistor is used to demonstrate heating effects. Self heating effects can be modeled for any arbitrary device.

Temperature plot at the surface of the passivation oxide due to thermal heating of a buried interconnect aluminum line

External Heat Flow

Once the thermal output of the power devices has been analyzed at a device level, individual or numerous power devices sharing a common heat sink or package can be analyzed as simple heat sources using the Thermal 3D simulator in order to gauge how hot the package will get after final installation.

GaN HEMT device fabricated onto a Silicon Carbide substrate mounted onto a copper heat sink

Rev. 052008_05